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Semiconductor Memory Technologies Overview
Published in Shimeng Yu, Semiconductor Memory Devices and Circuits, 2022
Now the question becomes what is really scaling since the gate length no longer scales. To solve the ambiguity and better capture the nature of scaling, an alternative metric to evaluate the logic transistor density is proposed by using the contacted gate pitch (CGP)11 and the M1 pitch. Figure 1.14’s inset shows a simplified top-view layout of a FinFET-based logic standard cell. The CGP is the horizontal distance between the centers of the two adjacent gate contacts that are separated by a source/drain contact via. The M1 pitch determines the vertical dimension. Therefore, the effective area for one transistor is the product of the CGP and the M1 pitch. Since the gate length no longer scales today, what really scales is the CGP (with possibly reduced spacer distance between the gate and the source/drain contact vias). Figure 1.14 shows the scaling trend of the CGP and the M1 pitch below 45 nm in the past decade and the projection into 3 nm, 2 nm, and 1 nm nodes, indicating a straight downscaling trend with the slope to be extracted to be ~0.75× per generation till 7 nm node. As mentioned earlier, different companies have their own strategies in naming the node. Figure 1.15 shows the comparison between Intel and TSMC in the CGP and M1 dimensions in their recent nodes. It is seen that Intel’s 10 nm process is approaching TSMC’s 7 nm process in terms of integration density.
Efficient recursive least squares parameter estimation algorithm for accurate nanoCMOS variable gain amplifier performances
Published in International Journal of Electronics, 2020
Houda Daoud, Sawssen Lahiani, Samir Ben Salem, Mourad Loulou
A novel recursive least squares parametric estimation algorithm was proposed to minimise the error prediction given by the BW method and improve the estimation accuracy under the system complexity. The problem formulation was achieved relying on the adjustable model method and the least squares technique. The RLS algorithm was used to predict the CMOS transistor primary parameters for 16 nm to 10 nm process. An illustrative simulation example was presented to show the effectiveness of the proposed RLS algorithm. Comparing the PTM data to the RLS method, a satisfactory extrapolation with high efficiency and minimum relative error of the performed adjustment was achieved. The proposed RLS algorithm was used to predict the nanoCMOS performances of the VGA circuit which was optimised through the Heuristic program. The Nanoscale CMOS can drop the power consumption of the VGA circuit below 50 µW value favouring the very low power future wireless systems. The deep-submicron CMOS process has the advantage of maintaining the device and circuit speed improvements despite the shrinking supply voltages. Our future potential works will involve the use of the proposed RLS method to predict the performance of new VGA topologies useful for new radio-communication receivers.