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Nanotechnology Advances, Benefits, and Applications in Daily Life
Published in Cherry Bhargava, Amit Sachdeva, Nanotechnology, 2020
Nanotechnology answers calls for how we can improve the proficiency of electronic procedures, by decreasing their weight and power utilization. It has significantly contributed to the growth of the IT industry. It has entrusted the expansion of smaller, faster, and more portable systems. The transistors that facilitate all recent computing are becoming smaller and smaller, leading to the storage of superior memory on a small chip. Some transistor developments of nanotechnology are Intel, producing a 14 nm transistor (2014), IBM, the first 7 nm (2015), and the 1 nm transistor at the Lawrence Berkley National Laboratory (2016).
2.5D/3D ICs
Published in Aida Todri-Sanial, Chuan Seng Tan, Krzysztof Iniewski, Physical Design for 3D Integrated Circuits, 2017
Beginning with the invention of integrated circuits (ICs) in 1959, higher computing power was achieved primarily through density scaling and commensurate performance enhancement of transistors as a result of continuously scaling down the device dimensions in a harmonious manner. This has resulted in a steady doubling of device density from one technology node to another [1]. This observation was famously known as “Moore’s Law,” first coined by Carver Mead of Caltech. The scaling law was based on a set of rules proposed by Robert Dennard of IBM [2]. Improvement in transistor switching speed and density are two of the most direct contributors to the historical performance growth in ICs (particularly in silicon-based digital CMOS). This scaling approach has been so effective in many aspects (performance and cost) that ICs have essentially remained a planar platform throughout this period of rigorous scaling. In the recent years, pitch scaling is augmented with a number of performance boosters such as strain engineering, high-κ/metal gate, and nonplanar 3D transistors. At the time of this writing, the industry is already manufacturing the 16/14 nm node devices. There is a consensus that geometrical scaling cannot be sustained indefinitely as the manufacturing cost will be prohibitively high. The industry is actively exploring several promising options. The focus of attention is on “system scaling” and 2.5D/3D integration has been favorably singled out. Several “low hanging” products that leverage on slim form factor and high density afforded by 3D integration, such as CMOS image sensor and memory stack, are already in the market. It is anticipated that the next phase of development will deliver high-bandwidth memory/logic stack and heterogeneous systems to meet the insatiable demands.
The Driving Forces Behind Moore’s Law and Its Impact on Technology
Published in Lambrechts Wynand, Sinha Saurabh, Abdallah Jassem, Prinsloo Jaco, Extending Moore’s Law through Advanced Semiconductor Design and Processing Techniques, 2018
Lambrechts Wynand, Sinha Saurabh, Abdallah Jassem
These listed items contribute significantly to an increase in semiconductor manufacturing cost, which can undermine savings in cost per unit area of semiconductor materials. The financial benefits of being at the forefront of technological progress in the electronics industry provided the motivation for the semiconductor industry to formalize the predictions from the Moore’s law model as objectives that the industry should strive to meet. These objectives, or nodes, were the common denominators used as competition guidelines between industry leaders, while they continually attempted to keep up with Moore’s law. Thus, the actions of key players in the semiconductor industry made Moore’s law a self-fulfilling prophecy. The critical economic aspect contained in Moore’s law is that, as technology evolves and advances to new heights, a larger amount of functionality can be offered at the same cost associated with a particular component count and cost (Hutcheson 2009; Sullivan 2007). The complexity of modern electronic circuitry has created significant technical and economic challenges at the manufacturing level, such that the economic factors of modern-day production of ICs are no longer as attractive as in the past (Mack 2011). Expensive additional steps and equipment are required to reliably manufacture recent nodes, such as 22 nm or 14 nm nodes, with additional costs for processes such as package-on-package and through-silicon via packaging requiring costly and specialized equipment and operator skills. These issues have caused a slowing down in transistor scaling, superseded in many ways by the development of new and innovative techniques to increase yield and reliability and bring down the cost of production. It is also a common notion for foundries to purchase or transfer older technologies, especially 350 nm and 180 nm nodes, and to provide specialized services such as low minimum-order quantity options for research institutions or smaller companies aiming to develop ICs with higher complexity but with lower transistor count through innovation.
Impact of Interconnect Spacing on Crosstalk for Multi-layered Graphene Nanoribbon
Published in IETE Journal of Research, 2022
Vijay Rao Kumbhare, Punya Prasanna Paltani, Manoj Kumar Majumder
This subsection demonstrates the performance of coupled rough-edged MLGNR interconnect for different line spacing and interconnect length. The analysis is carried out for the proposed model using DIL setup as depicted in Figure 6 at 32, 22, and 14 nm technology. Using interconnect parasitics introduced in Tables 1 and 2, an efficient analysis is observed in terms of crosstalk-induced delay for diverse space as depicted in Figure 7(a), (b), and (c), at 32, 22, and 14 nm technology, respectively. Furthermore, it is evident that the signal transition period (delay under crosstalk) increases for interconnect length ranges from 100 to 1000 µm while it is reduced for increasing the space between the coupled interconnects. It is evident due to the rise in the quantitative value of interconnect parasitics for longer interconnects that significantly increases the delay under the influence of crosstalk. However, at a particular technology node, the impact of crosstalk reduces for more interconnect spacing due to a reduced coupling capacitance as observed from (19). As demonstrated in Table 2, the quantitative value of coupling capacitance reduces for more spacing using 14 nm technology in comparison to 32 and 22 nm, that is the major cause for improved crosstalk-induced delay.
Is India going to be a major hub of semiconductor chip manufacturing?
Published in IETE Technical Review, 2021
The inflection point for cost reduction came around 14 nm technology node. As compared to previous technology nodes, the cost per transistor is higher for nodes below 14 nm due to high equipment price and uncertainty in yields. At these nodes, we are forced to use techniques such as electron beam lithography for patterning on silicon which is expensive and also is a poor cousin of optical lithography in terms of throughput i.e. the number of wafers that can be processed per hour.