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Data Converters
Published in Wai-Kai Chen, Analog and VLSI Circuits, 2018
With the increased complexity possible in modern-day integrated circuits, analog-to-digital converter (ADC) and digital-to-analog converter (DAC) have become ubiquitous components of mixed-signal integrated circuits. ADCs transform an analog signal, VA, into an N-bit digital representation, Vd. Such a converter is said to have a resolution of N bits. The digital signal Vd is an approximation of the original analog signal, VA, and the maximum error during this conversion process for an N-bit converter is equal to 1/2N of the full-scale value. This error is called the quantization error.
CMOS Analog and Mixed-Signal Circuit Design
Published in Arjuna Marzuki, CMOS Analog and Mixed-Signal Circuit Design, 2020
The analog circuit employs the analog signal, while the digital circuit employs the signal that is defined only at discrete values of amplitude. A mixed-signal integrated circuit is a combination of analog and digital integrated circuits. This book proposes the concept of a signal path idea for circuit design insight. This book covers the practices and research topics of the analog and mixed-signal integrated circuits.
Force-System Resultants and Equilibrium
Published in Richard C. Dorf, The Engineering Handbook, 2018
Advances in the processing technology of analog integrated circuits have led to circuits offering higher speeds, greater power outputs, and greater precision. Also mixed-signal integrated circuits with a combination of analog devices and digital devices have become more important, offering the possibility of having an entire electronic system on a chip.
A 1.8 V 8.62 µW Inverter-based Gain-boosted OTA with 109.3 dB dc Gain for SC Circuits
Published in IETE Journal of Research, 2019
Yajunath Kaliyath, Tonse Laxminidhi
Switched capacitor circuits are used in the discrete-time implementation of most of the analog and mixed signal integrated circuit (IC) designs such as filters and modulators [1,2]. An OTA is the basic building block in a SC circuit and it accounts for a large fraction of the total power consumed by the IC. Further, the dc gain of an OTA determines the accuracy of charge transfer in the SC circuits [2]. So, SC circuits require an OTA that offers a high dc gain in order to ensure an accurate charge transfer. Folded-cascode topology has been the preferred choice for OTA implementation, as it offers a high dc gain; but, they consume a lot of power when operated at higher supply voltages [3–5]. Recently, inverter-based OTA's have been reported to replace the traditional OTA's in SC applications [6–8]. Design simplicity, area efficiency and power efficiency (at lower supply voltages) are the main advantages of an inverter-based OTA. However, these inverter-based OTA's are suitable for only low voltage applications ( V) because they consume a lot of power when operated at higher supply voltages ( V) [6,8].
Design of self-biased folded cascode CMOS op-amp using PSO algorithm for low-power applications
Published in International Journal of Electronics Letters, 2019
Hassan Jassim Motlak, Mohammed Jasim Mohammed
The device that has become one of the most diverse and important building blocks in analog circuit design is the operational amplifier. The operational amplifier is a high-gain direct-coupled amplifier usually include one or more differential amplifiers followed by a level transistor and output stage (Yadav, 2012; Azmi and Sunil Suresh (2014). For analog circuit design in a mixed-signal system, the complementary metal-oxide semiconductor (CMOS) technology has become dominant over bipolar technology due to the industry trend of applying standard process technologies to implement both analog circuits and digital circuits on the same chip (Mishra & Nema, 2013). Several CMOS op-amps are designed in literatures (Farahmand & Shamsi, 2012; Patel & Thakker, 2016; Prajapati & Shah, 2015; Srinivas, Balaji, & Padma Sree, 2016; Vural, Erkmen, Bozkurt, & Yildirim, 2013; Vural & Yildirim, 2012) to optimise the performance parameters of CMOS op-amp. Genetic algorithm used to optimal dimensions of each transistor to improve op-amp performance for analog and mixed signal integrated circuit design (Srinivas et al., 2016). Modified particle swarm optimisation (PSO) algorithm-based optimiser for automatic circuit design. The performance of the modified PSO algorithm is compared with two other evolutionary algorithms, namely, ABC algorithm and standard PSO algorithm by designing two-stage CMOS operational amplifier (Patel & Thakker, 2016). An efficient optimization methods for sizing a differential amplifier with current mirror load. The aim is to minimise MOS transistor area using three evolutionary algorithms, differential evolution, artificial bee colony algorithm and harmony search (Vural, Erkmen, et al., 2013, Vural & Yildirim, 2012). PSO algorithm has been used for the optimum design of CMOS analog circuits with high optimisation skill in small computational time. Parameter values obtained from PSO algorithm are verified using spice circuit simulator. In this work, C code of PSO algorithm has been interfaced with Ngspice circuit simulator for circuit optimisation (Prajapati & Shah, 2015). Investigates nature-inspired met heuristics for optimised sizing of a CMOS comparator with PMOS input driver. The aim is to minimise MOS transistor area using two nature-inspired met heuristics, differential evolution and harmony search (Vural, Bozkurt, & Yildirim, 2013). A novel folded cascode operational amplifier is proposed which improves DC-gain using positive feedback technique (Farahmand & Shamsi, 2012).