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RISC Architecture
Published in Pranabananda Chakraborty, Computer Organisation and Architecture, 2020
ARM is a 32-bit processor with both its data words and address words of 32 bits long. This processor has a total of 37 registers, out of which 15 registers labelled R0 through R14 are GPRs and R15 is the program counter. Of these registers, R0 through R7 and R15 are visible, and are shared by all modes. The other 15 GPRs called banked registers are used at the time of process switching or context switching. The remaining six are the program status register. The contents of these registers are, however, available to the user, even in the system modes. The current program status register (CPSR) holds the condition code flags. Apart from user mode, ARM provides several other privileged modes, such as supervisor mode, abort mode, undefined mode, fast interrupt mode, and interrupt mode, for various exception handling. The ALU employs a combinational logic for addition and subtraction, and a combinational shift circuit using sequential shift-and-add method for multiplication and other operations. A separate address–incrementer circuit realizes address–manipulation operations such as PC: = PC + 1, independently of the ALU. A barrel shifter is provided for fast shift operation with a large number of shifts using a single instruction.
Digital Signal Processors
Published in Nihal Kularatna, Electronic Circuit Design, 2017
Increasingly, many DSPs feature a barrel shifter and instructions that use the barrel shifter to perform arithmetic or logical left or right shifts by any number of bits. Examples include the AT&T DSP16xx, the Analog Devices ADSP-21xx and ADSP-210xx, the DSP Group Oak DSP Core, the Motorola DSP563xx, the SGS-Thompson D950-CORE, and the Texas Instruments TMS320C5x and TMS320C54x. If one begins with a 16-bit input, a complete set of shifting functions needs a 32-bit output. These functions include arithmetic shift, logical shift, and normalization. The shifter also performs derivation of exponent and derivation of common exponent for an entire block of numbers. These basic functions can be combined to efficiently implement any degree of numerical format control, including full floating point representation. Figure 7.16 shows a block diagram of the ADSP-2101 shifter.
Basics of the central processing unit
Published in Joseph D. Dumas, Computer Architecture, 2016
Notice that control inputs (which are output from the processor’s control unit) are used to select which arithmetic or logical function the ALU and shifter perform at any given time. One of the ALU functions may be simply to transfer one of the operand inputs to the output without modification; this allows the shifter to operate directly on register contents and provides for simple register-to-register transfers via the datapath. The shifter has the ability to pass bits through unchanged, or move them to the left or right, either by one position or many (as in the case of a barrel shifter) at a time. Also notice that the ALU typically develops “condition code” or status bits that indicate the nature of the result produced (positive/negative, zero/nonzero, the presence or absence of an overflow or carry, etc.). The bitwise logical functions of the ALU are trivial to implement, requiring only a single gate of each desired type per operand bit; shifting is not much more complicated than that. The real complexity of the datapath is in the circuitry that performs arithmetic calculations. We devote the rest of this section to a closer look at integer arithmetic hardware.
Unsupervised image thresholding: hardware architecture and its usage for FPGA-SoC platform
Published in International Journal of Electronics, 2019
Jai Gopal Pandey, Abhijit Karmakar
To compute the fractional value of the binary logarithmic, the remaining bits are provided to a barrel shifter circuit, which is shown in Figure 11. It is composed of two 31-bit, 8-to-1 multiplexer, and one 31-bit, 2-to-1 multiplexer. The barrel shifter circuit provides selection bits for the FPA circuit. The selection process for the required bit shifting in the barrel shifter circuit is shown in Table 2. As explained in Table 2, the 16-bit LOF circuit provides the 4-bit output, the MSB of 4-bit S[3], selects the rightmost multiplexer. The rest 3 output bits of the LOF16, i.e. S[2:0] are used to select the 16 inputs. These inputs are provided to two 8-bit multiplexers. Here, S[2:0] is provided to the select lines of two multiplexers. Depending upon the bit value of S[3], any one of the multiplexer is selected, and it routes input to the output as per Table 2. The output of the barrel shifter circuit is connected at the input side of the FPA unit. The detailed circuit description of the FPA unit is explained below.
Elementary operations: a novel concept for source-level timing estimation
Published in Automatika, 2019
Nikolina Frid, Danko Ivošević, Vlado Sruk
Xilinx Zynq ZC706 reconfigurable evaluation board has been chosen as target platform. Three configurations, each composed of one processor and one memory element have been used: MB1 – MicroBlaze, a 32-bit RISC Harvard architecture soft processor core in the following configuration: 5-stage pipeline with hardware multiplier, barrel shifter and floating-point unit operating at 200 MHz. The processor is connected to 128 KB FPGA-based BRAM memory, operating also at 200 MHz, via local memory bus (LMB). This memory is used for storing both instructions and data.ARM1 – A single core of ARM Cortex-A9 processor is used in the following configuration: operating frequency at 667 MHZ, 32 KB L1 cache and 512 KB L2 cache with both instructions and data stored in DDR3 SDRAM memory operating at 533 MHz.ARM2 – A single core of ARM Cortex-A9 processor is used in the following configuration: operating frequency at 667 MHZ, 32 KB L1 cache and 512 KB L2 cache but the instructions were stored in DDR3 SDRAM operating at 533 MHz and data is stored in 128 KB FPGA-based BRAM memory operating at 200 MHz.