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Digital theory, logic, and two-state control
Published in Raymond F. Gardner, Introduction to Plant Automation and Controls, 2020
Whereas combinational logic uses discrete condition-based input signals, sequential logic follows a series of events, and to function, it requires memory of its previous output. Sequential logic can be event driven, clock driven, or pulse driven. Figure 4.9shows a general functional block diagram of sequential logic. Event-driven sequential logic uses an external signal, such as a hand- or pressure-actuated switch, to change the output logic state when toggled, and is called asynchronous since it is independent of a clock.Clock-driven sequential logic is synchronized to a clock, which obtains its triggering function from a timer circuit.Pulse-driven sequential logic uses both event- and clock-driven triggering inputs. The toggling that would normally happen with an input-signal switch must occur simultaneously with a clock-driven signal obtained from a timer circuit. When both the input signal and clock signal occur, the output logic state can be triggered to a new state.
C
Published in Philip A. Laplante, Comprehensive Dictionary of Electrical Engineering, 2018
comb filter an electric wave filter that exhibits an amplitude versus frequency plot of periodically spaced pass bands interspersed with periodic stop bands. This plot resembles the teeth of an ordinary hair comb, from which the filter derives its name. comb-line filter filter consisting of parallel coupled transmission line resonators where all resonators are grounded on one side and capacitively loaded to ground on the other. Adjacent resonators are grounded on the same side. When fabricated as strip conductors in microstrip or stripline form, the metalized patterns have the appearance of a comb. comb function a function made of evenly spaced, equal amplitude time or frequency components (the Fourier transform of the comb function is another comb function). The comb function is useful for discretizing continuous signals and can be represented as the infinite sum of delta functions evenly spaced through time or frequency. combination tone various sum and difference frequency that are generated when two intense monochromatic fields interact with the same semiclassically described laser medium. combinational lock interconnections of memory-free digital elements. combinational logic a digital logic, in which external output signals of a device are totally dependent on the external input signals applied to the circuit. combined cycle plant a gas-turbine power plant in which the exhaust gases are used to heat water in a boiler to provide steam to run a turbogenerator. combined field integral equation (CFIE) a mathematical relationship obtained by combining
Combinational Logic
Published in Joseph Cavanagh, Digital Design and Verilog HDL Fundamentals, 2017
A combinational logic circuit is one in which the outputs are a function of the present inputs only. The operation of combinational logic circuits can be expressed in terms of fundamental logical operations such as AND, OR, and NOT (Invert). The output f of an exclusive-OR operation with inputs x1 and x2 is described as f = x1x2′+ x1x2′, which is read as “(x1 AND NOT x2 ) OR (NOT x1 and x2 ).” The outputf of an exclu-sive-NOR operation with inputs x1 and x2 is described as f = x1x2 + x1′x2′, which is read as “ (x1 AND x2) OR (NOT x1 AND NOT x2 ).”
An efficient design of CORDIC in Quantum-dot cellular automata technology
Published in International Journal of Electronics, 2019
Ismail Gassoumi, Lamjed Touil, Bouraoui Ouni, Abdellatif Mtibaa
Figure 15(b) illustrates the proposed QCA Flip-Flop. It includes 79 cells with an area of 0.15 µm2. It takes five clock periods for the inputs to reach the output and first meaningful output comes on sixth clock. The multiplexer (MUX) is a combinational logic circuit designed to commutate one of the various input lines to a single output line by the application of a control signal. The logic implementation of a 2:1 MUX can be done by using three Majority gates and one inverter gate. Its schematic and QCA layout is shown in Figure 16(a,b) respectively. The proposed MUX consists of circuit area of 0.17 µm2, circuit complexity of 75 cells and requires 5 clock phases to generate the correct output.
Design and comparative analysis of memristor-based transistor-less combinational logic circuits
Published in International Journal of Electronics, 2022
Md Hasan Maruf, Md Shakib Ibne Ashrafi, A. S. M. Shihavuddin, Syed Iftekhar Ali
The combinational logic circuit is one of the key factors for designing any digital circuit application. Some important building blocks of combinational logic circuits are binary adder and subtractor, decoder, encoder, multiplexer, coder converter, etc. All of these circuits use CMOS technology for designing their logic gates. The novel objective of this paper is to design these logic gates using only a memristor where no transistor is being used. The proposed memristor-based design technique can be found effective in terms of area, power consumption, and delay because of less transistor count.
Characterization of Test Sets for Multiple Faults in Combinational Network
Published in IETE Journal of Education, 2021
The problems of determining whether a digital circuit operates correctly or not are both of practical importance and theoretical concern. Combinational logic circuits form the vital parts of a digital system. Hence fault detection of combinational logic circuits has received much attention. One way of knowing whether a combinational logic circuit with n primary inputs operates correctly is by applying to the circuit all possible 2n primary input patterns and comparing the resultant primary outputs with those given by the corresponding truth table of the fault-free version of the same circuit. If there exists a conflict for at least one of the 2n primary input patterns, then a fault exists in the network. Otherwise, the network will be fault free. Such an exhaustive testing of a combinational network will be very much time-consuming in case of a complex circuit. To address this problem, algorithmic test pattern generation [1–8], has been developed. Most of the well-known fault detection techniques are based on stuck-at fault model according to which the fault on a line of a combinational circuit can be either stuck-at-zero () or stuck-at-one (). Techniques based on single stuck-at fault model as well as multiple stuck-at fault model are available in the literature. It is recognized that multiple fault testing is not usually worth the effort since single fault testing catches the faults all at a time. However, there exist some works on multiple fault testing [4, 5, 8]. Among them, there are some heuristic techniques [4, 5] based on the notion of Boolean differences. Boolean difference [3, 5–7] is a straight forward and analytical tool for fault detection. The first-order Boolean difference (denoted by ) of the Boolean function with respect to , is defined as This definition of first-order Boolean difference can then be extended to obtain various higher order Boolean differences, the p-th order Boolean difference of the Boolean function being defined as