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Impact of Semiconductor Materials and Architecture Design on TFET Device Performance
Published in Shubham Tayal, Abhishek Kumar Upadhyay, Deepak Kumar, Shiromani Balmukund Rahi, Emerging Low-Power Semiconductor Devices, 2023
M. Saravanan, Eswaran Parthasarathy, J. Ajayan, D. Nirmal
TFET is mainly used for low-power devices, and for its application, we employ band-to-band tunnelling (BTBT). By comparing with the structure of MOSFET, it contacts surfaces showing variation in the opposite doping polarity. In the source region of TFET based on different polarities, in nTFET, the source region is the p-type, and for pTFET, the source region is the n-type. There are several variants of the fundamental design, such as various gate overlaps or doping profiles. In doping the TFET, the Fermi level is associated with the valence band edge of the source region [5]. The TFET works by controlling the electrostatic potential at these places via the gate contact, permitting and opposing BTBT tunnelling among source and channel regions. The connection is given as reversed as in the source and drain, and it stimulates the diode to work on reverse as shown in Figure 5.2. In the diode, current flows in reverse leakage in the OFF condition, and this occurs often due to the diffusion current of the minority charge carrier.
Fundamentals of TFETs and Their Applications
Published in Balwinder Raj, Ashish Raman, Nanoscale Semiconductors, 2023
V. Ramakrishna, A. Krishna Kumar
The tunneling effect is a common phenomenon when transistors are shrunk to the nanoscale size. Most of the negative effects that accompany transistors are mostly negative effects. A TFET is the application of the principle of tunneling as a mechanism for controlling the switching of transistors and has been regarded as a very promising element in recent years. The reason is that a TFET is different from the operating mechanism of MOSFET, so it can avoid many short channel and reliability problems encountered when shrinking the size. A TFET has an SS of less than 60mV/dec and a very small leakage current. These features are conducive to the miniaturization of VD and reduce the problem of energy consumption, so it is suitable for application in low-power components. However, TFET also has some problems that need to be overcome, such as low on-state current value, high concentration of doping, and high accuracy of doping position. These are the goals that need to be solved when developing TFETs in the future.
MOSFET Design and Its Optimization for Low-Power Applications
Published in Suman Lata Tripathi, Parvej Ahmad Alvi, Umashankar Subramaniam, Electrical and Electronic Devices, Circuits and Materials, 2021
P. Vimala, M. Karthigai Pandian, T. S. Arun Samuel
Many optimization methods have been proposed [25] to overcome the constraints of reduced ON current such as DG TFETs, DMDG TFETs, SG TFETs, high-k gate dielectric TFETs, strained-SiGe TFETs, and heterojunction TFETs. Together with silicon, germanium and III–V semiconductor materials are often considered as valid materials for the manufacture of TFET devices due to the lower value of the direct energy band gap. For all these methods, exponentially increasing ON current has been achieved using the BTBT electron generation rate, which depends on the energy band gap of the source and channel material, width of the tunneling barrier, gate oxide thickness, and effective mass of the charge carrier. Similarly, the simple way of reducing the ambipolar behavior of TFETs is to maintain source doping higher than drain doping. However, different optimization methods have been proposed to overcome the ambipolar behavior of TFETs such as heterogate dielectric TFETs, gate drain over/under lap structures, and asymmetric device structures.
Sentaurus TCAD simulation of SET and Radiation-Hardened technology for FDSOI TFET devices
Published in Radiation Effects and Defects in Solids, 2023
Shougang Du, Hongxia Liu, Shulong Wang
All of the above methods are based on the traditional physical mode of hot carrier injection and do not fundamentally break through the physical limitation of traditional devices in subthreshold swing. The tunneling field effect transistor (TFET) uses the physical mechanism of band tunneling (17, 18) to control the barrier width of the tunneling junction through the gate voltage, so as to realize the device switching. The TFET device has excellent electrical properties such as good subthreshold swing, high current switching ratio and low switching power consumption.
Design of universal logic gates using homo and hetero-junction double gate TFETs with pseudo-derived logic
Published in International Journal of Electronics, 2023
Lokesh Boggarapu, Sai Pavan Kumar K, Pown M, B Lakshmi
With the advancements in technology, scaling down of device dimensions is imminent to reduce power consumption and offer higher speeds of operation (Ratnesh et al., 2021)-(Dutta & Sarkar, 2019). The present metal-oxide-semiconductor field-effect transistor (MOSFET) technology becomes obsolete in lower scales of nanometre regime because of short channel effects (SCEs; Dutta et al., 2018)-(Talukdar et al., 2020). So, it is important to go for devices that can overcome SCEs and offer better performance in terms of power consumption and being capable of high-frequency operations. A tunnel field effect transistor (TFET) is one such device famous for its steep subthreshold swing, lower threshold voltage and lower leakage current. Having a steep subthreshold swing (SS) proves to be useful in many low-power applications such as dynamic random-access memory (DRAM; Khatami & Banerjee, 2009). Also, the leakage current reduction leads to the production of a higher ION/IOFF ratio, which is of high significance in low power-integrated circuits. The band-band tunnelling (BTBT) mechanism in TFETs is one of the key factors responsible for the charge carriers to have high mobility and increased current density whilst crossing junction reducing chances of recombination, which usually occurs in MOSFET (Baravelli et al., 2014; Turkane & Kureshi, 2016; Villalon et al., 2014). The structure of TFET being like that of MOSFET can also make it easier for device fabrication to transition from MOSFET to TFET (Villalon et al., 2014). Although the transition is smoother in theory, still TFET technology has demerits such as low ION as the device depends on several factors like BTBT, effective mass of carriers, bandgap alignment dependance of the oxide thickness on the channel length and many factors (Anghel et al., 2011; Boucart & Mihai Ionescu, 2007; Duan et al., 2018; Khatami & Banerjee, 2009). However, such limitations can be removed with the current research with the usage of homojunction Si TFETs and usage of different materials and high-k dielectric oxides in heterojunction TFETs (Barboni et al., 2015; Dewan, 2020; Morris et al., 2014). Materials include binary and tertiary semiconductors, such as SiGe, InAs, GaSb and InGaAs, which can provide a higher rate of tunnelling by band bending at lower voltages. Although much research is being performed in realisation of TFETs, the simulations are still behind the experiments being performed. It is observed that not only the materials of the device but also the structural improvements are necessary for increasing the compatibility between simulation and experiments (Cem et al., 2017; Nirschl et al., 2004; Wei et al., 2017).
Electrostatically Doped Schottky barrier tunnel field effect transistor
Published in International Journal of Electronics Letters, 2022
Harendra Kumar, Sangeeta Singh, Kumari Nibha Priyadarshani
In the semiconductor industry, scaling is the major challenge for conventional CMOS structure. Scaling approaches for sub-45-nm regimes create many aggravate problems of extremely degraded device performance and gate leakage (Shalf, 2020). However, at present time, semiconductor industrial trends are highly focused on low power, low cost, low area and high performance device. The magnificent improvements over the decades have enabled huge thrive in semiconductor industries to innovate the advanced structures. This results in the actual realisation of beyond 10-nm technology nodes where conventional structures are limited by the short channel effects (SCEs) and other fundamental limitations (Sakurai, 2004). This motivates the innovative MOSFET structures for greatly scaled dimensions like Schottky barrier MOSFET (SB-MOSFET) as an alternative to conventional MOSFETs. Another crucial limitation of these thermionic emission-based MOSFET carrier transport mechanism is higher sub-threshold slope (SS) (Guin et al., 2014; Guo & Lundstrom, 2002; Jhaveri et al., 2009; Kim et al., 2011; Zhang et al., 2007, 2005). To resolve this, tunnel field effect transistors (TFETs) are explored extensively, however, TFETs demonstrated very low drive current. To increase the ON current of TFET, the use of germanium and III–IV semiconductor materials in the source, pocket etc. (Boucart and Ionescu, 2007; Ionescu & Riel, 2011; Li & Woo, 2018; Saurabh & Kumar, 2010; Seabaugh & Zhang, 2010; Theis & Solomon, 2010) has been demonstrated. Further, at ultra-scaled dimensions, electrostatically doped transistors are introduced owing its ease of fabrication. As it does not need ion implantation/diffusion to realise the ultra-sharp source/drain doping profile. In addition to this the electrostatically doped transistors are resilient for the random dopant fluctuations (RDFs) and bulk trap-assisted tunnelling (TAT)-induced degradation. The concept of electrostatic doping is explored for its various aspects (Kaity et al., 2020; Kumar et al., 2020; M.J. Kumar & Janardhanan, 2013; Rajasekharan et al., 2010; Singh & Kondekar, 2017; Singh et al., 2016). These concurrent findings envisioned authors to investigate electrostatically doped schottky barrier tunnel field effect transistor (ED-SB-TFET). In this manuscript, we have extended the electrosatic doping concept to asymmetric schottky barrier tunnel field effect transistor as well by deploying the work-function engineering of the drain electrode. The analysis presented in this report depicts an idea of realising the schottky barrier tunnel field effect transistor even without the actual metallurgical doping. Hence, the reported structure offers immunity towards random dopant fluctuations (RDFs), process variations, doping control issues, and bulk trap-assisted tunnelling (TAT)-induced degradation. In addition to this, the analog and RF performance parameters have also been analysed here. This device demonstrates the gate-controlled schottky tunnelling at the source side and spacer is used to reduce the fringing field on the schottky barrier and also increase the channel length, it improves the drain-induced barrier lowering (DIBL) and also device performance.