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Effect of Ground Plane and Strained Silicon on Nanoscale FET Devices
Published in Brajesh Kumar Kaushik, Nanoscale Devices, 2018
Saurabh Chaudhury, Avtar Singh
To realize the FD SOI MOSFETs in nano-regime, two device issues are most important. Firstly, we must have less drain-induced barrier lowering (DIBL); and secondly, the subthreshold slope must be very steep. In long-channel SOI MOSFET, the subthreshold slope can be improved by increasing the BOX thickness. In a short-channel SOI MOSFET, on the other hand, a thicker BOX causes a larger DIBL due to the electric field penetration through the BOX. Due to this, the subthreshold slope worsens with an increase in the BOX thickness. Ground plane (GP) concept is one of the techniques used to reduce the DIBL effect, and it is quite effective only when the distance between the ground plane and the drain is small compared to the channel length. Therefore, if the placing of the GP in the substrate (GPS) is to be done, then one should keep the BOX thickness as small as possible, but it will increase the subthreshold slope. Therefore, in nanoscale devices with a very short channel length, it is not possible to achieve both reduced DIBL effect and steep subthreshold slope. By using GP in the BOX, it may be possible to reduce the aforementioned shortcomings; thus, the requirement of reduced DIBL as well as an improved subthreshold slope can be obtained [5,7] (Figure 3.5).
Impacts on Device Operation
Published in He Iwong, Nano-Cmos Gate Dielectric Engineering, 2017
The subthreshold characteristics are closely related to the interface properties of a MOS transistor (see Section 1.3.2). The subthreshold slope has become one of the most important figures of merits for a MOS transistor. Figure 5.12 depicts IDS-VGS characteristics of nMOS transistors with W/La2O3 and W/CeO2/La2O3 gate stacks at VDS = 0.05 and 1.2 V. The subthreshold slope was S = 101 mV/dec for the nMOS transistor biased at 0.05 V drain voltage. These results can be attributed to the high interface trap density as discussed in Section 5.3. The subthreshold slope can be improved significantly by introducing a CeO2 cap layer for oxygen chemical potential control [46]. As shown in Figure 5.12(b), the subthreshold slope was 72 mV/dec for the nMOS transistor with CeO2/La2O3 gate stack. These values are much better than the device using La2O3 only and should be mainly due to the reduction of interface charge density. Similar improvement was also found for the pMOS transistor. The subthreshold slope decreased from about 195 mV/dec (at VDS = 0.05 V) for La2O3 oxide to about 73 mV/dec for CeO2/La2O3 gate stack. X-ray photoelectron spectroscopy (XPS) measurement indicated that the as-deposited CeO2 was reduced to CeOx (a mixture of CeO2 and Ce2O3 phases) [47]. The reduction reaction of cerium dioxide is given by
Novel Subthreshold Modeling of FinFET-Based Energy-Effective Circuit Designs
Published in Balwinder Raj, Ashish Raman, Nanoscale Semiconductors, 2023
Kavita Khare, Ajay Kumar Dadoria, Afreen Khursheed
Subthreshold slope (S) depends on the gate to source (VGS) of the transistor. It is defined as the amount of VGS required to change the subthreshold current by an order of magnitude. S=2.3Vtm, where m can be defined as m=1+3ToxWdep1+11ToxWdepe−πLeff/2Wdep+3Tox. The value of S, which is theoretically limited to 60 mV/dec at T = 300 K, should be as small as possible to ensure the steepest subthreshold characteristics.
Accurate Estimation of Data Retention Voltage (DRV) for a 6T SRAM Cell at 45 nm, 65 nm, and 130 nm Technology Nodes
Published in IETE Journal of Research, 2023
Ruchi Gupta, Mohit Goyal, S. Dasgupta
ni is defined as , where the denominator term is a constant. Assume ni to be the same for all transistors. The sub-threshold slope depends upon the W/L ratio and supply voltage of the transistor. For a particular supply voltage and W/L ratio the value of ni for the same type of transistor is constant, i.e. for PMOS transistors it can be taken as np and for NMOS transistors it can be taken as nn. Furthermore, for the same applied voltage nn or np is approximately the same for different cell ratios. We have taken the mean of nn and np as n over the corresponding CR.
Design and simulation of 3C-SiC vertical power MOSFETs
Published in International Journal of Electronics, 2021
The subthreshold slope is known to depend on the oxide capacitance and substrate doping (Muller & Kamins, 2003) resulting in an expected subthreshold ideality value of 1.8. However, this assumes a uniformly-doped bulk region with constant doping. For the simulated structure with a channel doping of 1017 cm−3 on top of a 1018 cm−3 bulk region, the capacitance per unit area is almost constant and independent of applied voltage as illustrated with 8. Assuming a capacitive divider and a 100 nm depletion layer width, one obtains a subthreshold ideality factor of 2.3 in good agreement with the value extracted from the simulated threshold curve. When fitted to a simple quadratic model, for which the drain current in saturation equals:
Ultra low power DG FinFET based voltage controlled oscillator circuits
Published in International Journal of Electronics, 2019
R. A. Walunj, S. D. Pable, G. K. Kharate
Even though the subthreshold region provides the advantage of achieving the ultra-low-power design, degraded performance and exacerbated variability are the major concerns of the subthreshold circuits. Devices with near-ideal subthreshold slope are optimal for subthreshold operation (Kim & Roy, 2004). FinFETs exhibits the near ideal subthreshold slope, small gate capacitance, higher Ion/I off ratio (Nirmal, Vijaya Kumar, Samuel, Jebalin, and Mohankumar 2012) and are therefore appropriate for subthreshold operation. The FinFET circuits have lower functional power supply and lower optimal energy consumption compared to bulk CMOS (Dadoria, Khare, Gupta, & Singh, 2017; Wu, Wang, & Xie, 2006). Moreover, FinFETs are promising alternatives to bulk CMOS in nanometer regime due to its immunity to SCEs and reduced process variability (Dadoria, Khare, Gupta, & Singh, 2017; Wu, Wang, & Xie, 2006).