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A Study of Leakage and Noise Tolerant Wide Fan-in OR Logic Domino Circuits
Published in Shilpi Birla, Neha Singh, Neeraj Kumar Shukla, Nanotechnology, 2022
Ankur Kumar, Sajal Agarwal, Vikrant Varshney, Abhilasha Jain, R. K. Nagaria
The subthreshold leakage is a current that flows from drain to source in weak inversion operation of MOS transistor [6, 7]. The subthreshold current is at its peak when the voltage difference between source and drain is equal to the power supply in a turned OFF transistor [8, 9]. In the present scenario, the subthreshold leakage is the predominant source of leakage current [36, 57], which is expressed by eq. (12.1)Isub=I0(1−e(−VdsVt))(e−Vgs−Vth0−ηVdsηVt)
Techniques for Power and Process Variation Minimization
Published in Christian Piguet, Low-Power Processors and Systems on Chips, 2018
Uneven and variable switching activity across the die and diversity of the type of logic, result in uneven power dissipation across the die. This variation results in uneven supply voltage distribution and temperature hot spots, across a die, causing transistor subthreshold leakage variation across the die. Supply voltage (Vdd) will continue to scale modestly by 15%, not by the historic 30% per generation, first, due to difficulties in scaling threshold voltage and second, to meet the transistor performance goals. Maximum Vdd is specified as a reliability limit for a process, and minimum Vdd is required for the target performance. Vdd variation inside the max–min window is plotted in Figure 1.12. This figure depicts a droop in Vdd, when IC current demand changes rapidly, which degrades the performance. This is the result of platform, package, and IC inductances and resistances that do not follow the scaling trends of CMOS process. Specifically, the time “0” point is relatively inactive, while a rapid change in power demand, by the processor leads to the large supply droop pictured. This problem is increased by good low-power design (e.g., clock gating). Power delivery impedance does not scale with Vdd and ΔVdd has become a significant percentage of Vdd.
Digital IC Design for Transceiver SOC
Published in Kaixue Ma, Kiat Seng Yeo, Low-Power Wireless Communication Circuits and Systems, 2018
Wang Yisheng, Kaixue Ma, Kiat Seng Yeo
Subthreshold leakage occurs when a CMOS gate is not turned off completely. For a good approximation, the leakage current value is given by Eq. (14.1) [21]: Isub=μ0CoxWL(m-1)(VT)2eVGS-VthmVT1-e-VDSVT, $$ I_{{sub}} = \mu _{0} C_{{ox}} \frac{W}{L}(m - 1)(V_{T} )^{2} e\left( {\frac{{V_{{GS}} - V_{{th}} }}{{mV_{T} }}} \right)\left( {1 - e^{{\frac{{ - V_{{DS}} }}{{V_{T} }}}} } \right), $$
Investigation of Adiabatic Logic in Nano-meter Technology
Published in International Journal of Electronics, 2023
Tarun Kumar Gupta, Shipra Upadhyay, Amit Kumar Pandey
In the past few decades, one of the major research topics in the electronics industry has become low-power VLSI circuit design. For getting required area and power performances, the length and width of transistors are shortened into the deep submicron regions. The divergence between the quickly growing portable electronic industry and slower development in battery technology forced the focus of VLSI designers in minimising the power consumed by the technique. In non-adiabatic logic techniques, energy directly depends on the square of the power supply (Roy et al., 2003). In such cases, voltage scaling is the preferable technique for reducing power consumption. Maximum reduction is only possible up to a certain point, though, as lowering the supply voltage for Complementory Metal Oxide Field Effect Transistor (CMOS) circuits results in decreased performance. Although scaling the threshold voltage can somewhat reduce performance loss, it causes a significant increase in subthreshold leakage current (Gonzalez et al., 1997).
Low leakage, differential read scheme CNTFET based 9T SRAM cells for Low Power applications
Published in International Journal of Electronics, 2022
This paper presents a Differential Read scheme-based 9T CNTFET SRAM cells with reduced Standby leakage power dissipation. It also presents the Architecture designed with a memory array of 4 × 4 size. The study shows that the two proposed designs achieve better Stability in read mode since it uses differential read scheme with isolated read and write ports. And also low standby leakage power dissipation is obtained by designing the cells such that to reduce the Subthreshold leakage which acts as the main component of the leakage current. Single bitline usage for performing the write operation makes the designs to consume less write dynamic power. The designs of this paper exhibit better performance in terms of Read power, Write power, Read Noise Margin and Standby Leakage power dissipation. Thus, in any Medical implantable devices where power consumption is of high priority as it relates to battery life and where accurate information seeking plays a crucial role, the designs of this brief will be a better choice.
A novel technique for static leakage reduction in 16 nm CMOS design
Published in International Journal of Electronics Letters, 2019
Subthreshold leakage can be reduced by increasing the threshold voltages of all devices in the design. But, this will significantly degrade the performance of the design. Therefore, greater threshold voltages are assigned to off devices which will reduce the leakage currents without much loss in performance. In order to reduce the gate tunnelling current, a greater value of oxide thickness is assigned to the off devices in the design. A PMOS device has gate leakage approximately 10 times lesser than NMOS transistor (Guindi & Najm, 2003). This is because hole tunnelling from the valence band is slower than the electrons tunnelling from the conduction band. In the previous studies like (Lee et al., 2003), the effect of I gate due to PMOS is ignored but in 16 nm short-channel device this effect cannot be ignored and accounts a significant portion of gate-tunnelling current. Subthreshold leakage current in a MOS device is given by the equation (Al-Hertani, Al-Khalili, & Rozon, 2008; Sharma, Pattanaik, & Raj, 2015):