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CMOS SOI Memory Design Technology
Published in Krzysztof Iniewski, Circuits at the Nanoscale, 2018
Kazutami Arimoto, Fukashi Morishita
Figure 5.15 shows the current-sense amplifier and word driver. Memory cells are connected to a negative voltage–VDD, whose voltage is supplied by the charge pump circuit via memory cell mirrors. The memory cell mirrors are arranged with the purpose of setting each read voltage of the bit line BL and the reference bit line RBL1, RBL0 at the value in the vicinity of 0 V. The write driver is driven with the supply voltage of 1/2VDD, and outputs 1/2VDD at “1”-write and 0 V at “0”-write. In addition, the write drivers leading to RBL1 and RBL0 lead to output “1” and “0” data, respectively. The sense amplifier includes a differential amplifier with two pairs of parallel inputs. The RBL1 voltage of VBL1 and the RBL0 voltage of VBL0 are input into one of the parallel inputs, and the BL voltage VBL is input as another parallel input. Because “1” and “0” data are always retrieved from RBL1 and RBL0, respectively, the relation of VBL1 > VBL0 is satisfied. In the case of “1”-read, VBL is equal to VBL1. Conversely, in the case of “0”-read, VB0 is equal to VBL0. VBL1, VBL0, and VBL are compared in the differential amplifier. The sense amplifier outputs the amplified storage data detecting this voltage difference with 4.3 ns after the WL activation.
Semiconductor Memory Circuits
Published in Vojin G. Oklobdzija, Digital Design and Fabrication, 2017
Sense amplifiers play a major role in the functionality, performance, and reliability of memory circuits. Sensing in semiconductor memory circuits means the detection and determination of the data content of a selected memory cell. A sense amplifier reduces the signal propagation delay from an accessed memory cell to the input of the next logic circuit, which needs to be driven by the contents of the memory cell being read. Sense amplifiers convert the arbitrary logic levels occurring on a bit line to the full swing rail-to-rail digital logic level required by the next stage digital circuit. The sensing may be “nondestructive,” when the data content of the selected memory cell is unchanged, as in SRAMs, 3T DRAMs, and ROMs, or “destructive,” when the data content of the selected memory cell may be altered, as in 1T DRAMs, by the sense operation. In general, the sense amplifiers perform the functions of amplification, delay reduction, power reduction, and signal restoration [1,8].
The Prospect of STT-RAM Scaling
Published in Xiaobin Wang, Krzysztof Iniewski, Metallic Spintronic Devices, 2017
Yaojun Zhang, Wujie Wen, Hai Li, Yiran Chen
For a fair comparison, the same sense amplifier structure is used in the simulations under different technology nodes. The ratio between the channel widths of the NMOS and PMOS transistors is maintained the same while the channel length of the transistors is adjusted according to the technology node. We define the sense margin as the voltage difference actually generated on the two inputs of the sense amplifier. A high sensing margin generally corresponds to a low sensing error rate. Because of the increased process variations, the sense margin of the sense amplifier must increase to overcome the device mismatch in the sense amplifier as the transistor feature size reduces. Figure 3.5(a) shows our simulation result of the sense margins at various technologies. When technology scales from 45 nm to 22 nm, the read currents (20% of IC0) decrease from 34 μA to 15 μA. The nominal sense margins generated from the STT-RAM cell are 17, 18, and 18.8 mV, respectively. Thanks to the improvement of resistance and TMR due to the adoption of perpendicular MTJ, the sense margin even slightly increases when the technology scales.
A Novel Design of 28 nm Latch Type Sense Amplifier for Differential Voltage Enhancement
Published in IETE Journal of Research, 2023
Yiping Zhang, Ziou Wang, Canyan Zhu, Lijun Zhang
Semiconductor foundries have been pushing for the limit of process scaling, projecting further technology advancement in device pitch, channel length and metal width. Consequently, consumer electronic products continue to benefit from improved device density, power efficiency and further cost reduction. On the other hand, much more design effort is required to maintain such momentum. For instance, a smaller channel length inevitably increases device variations, imposing challenges in the analog circuits and mismatch-sensitive design blocks. Furthermore, a smaller pitch leads to higher coupled signal interference. The induced noise has to be carefully addressed in designing high-frequency blocks. SRAM is an indispensable high-speed memory block on modern SoC. For its high-speed operation capability, a sense amplifier is commonly employed in memory blocks. Instead of relying on full-swing signals, the sense amplifier detects small differential voltage inputs and generates corresponding switch signal to avoid excess dynamic power and delay on passing bit-line voltages. However, the sense amplifier is vulnerable to differential noises in which coupling effect may play an important role.
Low leakage, differential read scheme CNTFET based 9T SRAM cells for Low Power applications
Published in International Journal of Electronics, 2022
Figure 25 shows the Architecture of SRAM with a of 4 × 4 memory array consisting of four rows and four columns. Each column consists of one Sense amplifier (Dobkin & Williams, 2011) for read purpose and a Write Driver for write operation. Sense amplifier is a key component of the read circuitry which is used to extract the data that is accumulated in the memory cell. It senses the signals of the bitlines which may be discharged to ground or charged to Vdd and amplifies the low voltage swing to a desirable level resulting a faster read operation. Write driver circuit provides the data which is to be written into the cell during write operation. The data provided to the Write driver circuit will be applied as input to the two complementary bitlines through which the data is entered into the cell. Since, the proposed designs of this paper use a single bitline to perform the write operation, a Write driver circuit to be used should be a single bitline one as mentioned in (Maroof et al., 2016). Each row consists of a WordLine Driver (Gupta et al., 2018) for selecting a read or write function. Wordline driver circuit is used to enable the read or write operation to be performed. As intended by the user to perform a read operation or a write operation, this circuit based on the input received from the decoder, enables the wordline of the selected cell and performs the action accordingly. One row decoder and one column decoder are used to choose a particular bit from the entire array. The requirement of using some application it is given an input address in the binary form. The received address enables a particular cell to be accesses from the entire array. The decoders used for implementing the architecture in this brief are designed with conventional cmos AND gates. The memory array of the architecture is designed with the two proposed cells as well as the existing cells. The remaining peripheral circuits used for the architecture are the conventional ones as mentioned earlier.