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Memory Organisation
Published in Pranabananda Chakraborty, Computer Organisation and Architecture, 2020
One of the limitations of standard SDRAM is that it can perform all its actions once per bus clock cycle, and that is at the rising edge of the clock signal. This drawback has been, however, alleviated by introducing a new version of SDRAM, referred to as double data rate SDRAM (DDR-SDRAM) that transfers data on both edges of the clock, i.e. twice per clock cycle; once on the rising edge of the clock pulse and once on the falling edge of it. DDR-SDRAM accesses the cell array in the same way that traditional SDRAM does. The latency of these devices is also the same as that of standard SDRAMs. But, since they transfer data on both edges of the clock, their bandwidth is essentially doubled for long burst transfers. To make this possible to work with data at such a high rate, the cell array is organised in two banks. Each bank can be accessed separately. Consecutive words of a given block are stored in different banks. Such interleaving of words allows simultaneous access to two consecutive words located in two different banks that can now be transferred on successive edges of the clock. The concept of interleaving of memories, however, are discussed in Section 4.8.2 in more detail.
Force-System Resultants and Equilibrium
Published in Richard C. Dorf, The Engineering Handbook, 2018
SDRAM, the current-volume industry-standard DRAM has several advantages over FPM/EDO. First SDRAM operates synchronously with the system clock increasing performance, and provides flexible programmable block access modes to control burst length and column access order. In addition, the internal architecture of SDRAM supports a multiple bank organization. The separate banks can be controlled so that while one bank is being read, another can be primed by activating its RAS, an operation known as precharging. Consequently, different rows can also be accessed in burst mode as long as they reside in different banks, resulting in high memory bandwidth. DDR SDRAM is similar to SDRAM, but doubles the memory bandwidth by transferring data twice per clock cycle, at both the rising and falling edges of the clock.
The PC
Published in Mike Tooley, PC Based Instrumentation and Control, 2013
Synchronous DRAM (SDRAM) is a DRAM technology that uses a memory clock to synchronize signal input and output on a memory chip. The memory clock is synchronized with the CPU clock so the timing of the memory chips and the timing of the CPU are locked together. Synchronous DRAM saves time in executing commands and transmitting data, thereby increasing the overall performance of the computer. SDRAM allows the CPU to access memory approximately 25% faster than EDO memory.
Time-efficient fault detection and diagnosis system for analog circuits
Published in Automatika, 2018
Qiwu Luo, Yigang He, Yichuang Sun
This section puts forward the hardware scheme of the fault detection and diagnosis platform, its structure diagram is shown in Figure 1, the model of the main processor is XC3SD3400A (belongs to Spartan-3A DSP series, Xilinx). The signal generation part is consist of the digital to analog converter (DAC902, 165Msps/12-Bit) and the direct digital synthesizer (DDS) module. Then, the frequency sweep signal can be generated from SAM1 port, playing a role of the arbitrary signal source for analog circuit under test (CUT). When it comes to the data acquisition part, there are two different signal objects: for AC signals, we choose MAX12529, which is a dual channel signal acquisition chip owning high-performance up to 96Msps/12-Bit, hence the input/output signals of a certain circuit can be captured by this system through SMA2 and SAM3 respectively. For DC signals, in order to simplify design and enhance the flexibility, we developed it as sub-board form, so node voltage can be gathered through the interface of PIN array. As for the DSP cores being constituted with DSP48E slices, LUTs, dual-port block RAMs, and FIFOs, experimenters could rebuild them flexibly for their special design goal. In addition, the system is equipped with sufficient DDR2 SDRAM and Flash memories for computational variables and algorithm operation. Further, the raw gathered information and calculational data can be transmitted to remote host via the flexible Ethernet interface. A 32-bit embedded software processor, MicroBlaze, is used for global management.
A multi-objective optimization based on genetic algorithms for the sustainable design of Warm Mix Asphalt (WMA)
Published in International Journal of Pavement Engineering, 2022
Rodrigo Polo-Mendoza, Gilberto Martinez-Arguelles, Rita Peñabaena-Niebles
Undoubtedly, the execution time is affected by the characteristics of the development environment and the computer employed. Therefore, to simulate a non-advantageous case, non-professional everyday systems were used for this analysis. To be transparent, the specifications of these elements are listed below: Computer: Laptop with AMD Ryzen™ 7 3700U microprocessor, 8GB of DDR4 SDRAM, and a 512GB M.2 PCIe® NVMe™ solid-state drive.Development environment: an online tool with software acceleration disabled, i.e., neither graphics processing unit nor tensor processing unit was utilized.
Machine learning algorithms applied to intelligent tyre manufacturing
Published in International Journal of Computer Integrated Manufacturing, 2023
Simone Massulini Acosta, Rodrigo Marcel Araujo Oliveira, Ângelo Márcio Oliveira Sant’Anna
The measurement time of tyre attributes is every ten seconds. The company’s information system stored these measures in a database to be analyzed, allowing the process engineer to manage the finished products and the process parameters. The selected database covers a sample of 178 observations. The statistical summary of tyre weight (Kg) were minimum = 55.75, maximum = 58.35, mean = 56.80, standard deviation = 0.5598, and coefficient of variation = 0.96%. Simulations and calculations were performed with the open-source software R® (R 2021). All programs ran on a personal computer with an Intel Core i7-2670QM, 2.2 GHz, 8 GB DDR3–1333 SDRAM, Windows 7 Professional 64-bit.