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Advanced CMOS Devices on Bulk and SOI: Physics, Modeling and Characterization
Published in Simon Deleonibus, Electronic Device Architectures for the Nano-CMOS Era, 2019
Thierry Poiroux, Gilles Le Carval
To minimize the short channel effect on bulk MOSFETs, pockets are implanted below the LDD areas. These additional implanted regions are of the same type as the channel and contribute to flatten the threshold voltage versus gate length curve by two distinct effects. First, they limit the penetration of the electrical fields induced by the source and the drain into the channel, thus improving the electrostatic control by the gate. Second, because of these quite heavily implanted pockets near the source and the drain, the average channel doping is higher on short gate length. This induces a higher potential barrier between the source and the channel and thus a higher threshold voltage on short devices. This effect, known as reverse short channel effect, can be modeled by introducing a non uniform doping along the channel in the 2D Poisson equation and by using potential and field continuity equations to obtain the potential profile from the source to the drain and a closed form for the threshold voltage shift.4
Compact Models for Small Geometry MOSFETs
Published in Samar K. Saha, Compact Models for Integrated Circuit Design, 2018
This chapter presents compact MOSFET models for small geometry devices. In order to develop accurate small geometry compact model, the different structural and physical effects are modeled in device threshold voltage. First of all, the nonuniform substrate doping is modeled in device threshold voltage. Then the model for small geometry effects such as short channel effect, reverse short channel effect, narrow width and reverse-NWEs are included in the threshold voltage model. In this chapter, the accurate mobility model is derived to account for the effect of high gate bias on device performance. With accurate mobility model, the regional drain current models for the linear and saturation regions are developed to model high lateral electric field and velocity saturation due to high drain bias. Finally, the compact models for hot carrier–induced substrate current for MOSFETs devices are presented.
Carbon Doping of SiGe
Published in John D. Cressler, SiGe and Si Strained-Layer Epitaxy for Silicon Heterostructure Devices, 2017
A major challenge for the fabrication of ultrasmall devices for next silicon technology generations is the control of steep dopant profiles. In this context, it is tempting to apply supersaturated carbon as a diffusion-controlling agent in silicon. The fundamental question for applications of C-rich Si in devices is whether electronic device parameters are affected by possible C-related defects. Recently, Gossmann et al. [26] have announced the realization of MOSFET with reduced reverse short-channel effect due to suppressed transient diffusion in C-rich silicon. Little increase in leakage current was reported for devices with carbon. Successful applications of C-rich layers were reported for SiGe HBT [27,28]. The IHP group has demonstrated that transistors with excellent static and dynamic parameters can be fabricated with epitaxial SiGe:C layers [29,30]. The main result of this investigation was that carbon supersaturation can preserve steep boron doping profiles without degrading fundamental transistor parameters. The diffusion coefficient of B in Si is reduced by more than one order of magnitude when the concentration of substitutional C is elevated to about 1020cm–3 [31]. Furthermore, transient-enhanced diffusion (TED) of B is strongly suppressed in C-rich Si [32].
Robust low power transmission gate (TG) based 9T SRAM cell with isolated read and write operation
Published in International Journal of Electronics, 2022
The reliability of 6 T SRAM cell reduces when operated at low voltage due to these PVT variations (Raychowdhury et al., 2005; Nezam et al., 2017). RSNM reduces at lower voltage operation of SRAM (Raychowdhury et al., 2005; Woong & Jongsun, 2016) because of the intrinsic read disturbance produced by the voltage division between the access transistor and the pull-down transistor. The write stability of the SRAM cell depends upon the size constraints of the access and pull-up transistors. Also the static noise margin (SNM) of SRAM is related exponentially with the threshold voltage (B. Calhoun & Chandrakasan, 2006) and shows a linear decline with a supply voltage reduction. Conventional 6 T SRAM cell lower operation till VDD equals to 0.7 V to 0.45 V (Meng-Fan et al., 2011). So, it is really difficult to use the 6 T SRAM cell in the subthreshold region (Hanwool et al., 2016) due to its frail write ability and reduced read stability (B. H. Calhoun & Chandrakasan, 2007). Read decoupled technique having a separate path for read operation (L. Chang et al., 2008) has been implemented for the read stability at the cost of extra transistors such as 8 T (Anh-Tuan et al., 2011; Khayatzadeh & Lian, 2014; Kulkarni et al., 2011; Sinangil et al., 2009; Tae-H. Kim et al., 2009; Tu et al., 2010; Verma & Chandrakasan, 2008; Wu et al., 2011), 9 T (Liu & Kursun, 2008; Woo et al., 2017) and 10 T (I. J. Chang et al., 2009; T.-H. Kim et al., 2008; Naeem & Bai-Sun, 2017). The reverse short channel effect (RSCE) with marginal bitline leakage compensation (MBLC) is used to improve the read and write margin in Tae-H. Kim et al. (2009). The authors in Sinangil et al. (2009) use dynamic voltage scaling and hardware re-configurability to design the SRAM. The data is isolated from the bitlines during read operation in Liu & Kursun (2008) to enhance read operation. A virtual ground replica scheme with RSCE is used in T.-H. Kim et al. (2008). Dynamic Differential Cascode Switch Logic (DCVSL) for enhancing read with bit interleaved architecture is employed in T.-H. Kim et al. (2008).