China
Africa
Explore chapters and articles related to this topic
CMOS Circuits
Published in Michael Olorunfunmi Kolawole, Electronics, 2020
This chapter starts by discussing the issue of noise, its sources and types, and how it affects the performance of CMOS. Afterwards, the constituents, configuration, fabrication, and design of CMOS into simple and complex logic circuits, as well as its formulation as transmission (or pass) gate and constitution into a VLSI chip are discussed. Also, the difference between static and dynamic CMOS transistors will be discussed. In the construction of static CMOS gate, two complementary networks are used, where only one of which is enabled at any time. Whilst duality is sufficient for static correct operation, it is not necessarily so in reality. The noise margin of a digital circuit or gate is considered: an indication of how well the circuit or gate will perform under noisy conditions. Pass-transistor logic implements a logic gate as a simple switch network. The optimal pass-transistor stages of buffered chain and its delay are derived for minimization.
CMOS Circuits
Published in Vojin G. Oklobdzija, Digital Design and Fabrication, 2017
Eugene John, Shunzo Yamashita, Dejan Marković, Yuichi Kado
In all the circuits we have discussed so far, the outputs are obtained by closing either the pull-up network to VDD or the pull-down network to ground. The inputs are used essentially to control the condition of the pull-up and the pull-down networks. One may design circuits in which the input signals in addition to VDD and VSS are steered to output, depending on the logic function being realized. Pass transistor logic implements a logic gate as a simple switch network. The pass transistor design methodology has the advantage of being simple and fast. Complex CMOS combinational logic functions can be implemented with minimal number of transistors. This results in reduced parasitic capacitance and hence faster circuits. As a pass transistor design example, Fig. 2.12 shows a Boolean function unit realized using pass transistors [3,7]. In this circuit the output is a function of the inputs A and B and the functional inputs P1, P2, P3, and P4. Depending on the values of P1, P2, P3, and P4, the F output is either the NOR, XOR, NAND, AND, or OR of inputs A and B. This is summarized in the table in Fig. 2.12.
Combinational and Sequential Design in CMOS
Published in Manoj Kumar Majumder, Vijay Rao Kumbhare, Aditya Japa, Brajesh Kumar Kaushik, Introduction to Microelectronics to Nanoelectronics, 2020
Manoj Kumar Majumder, Vijay Rao Kumbhare, Aditya Japa, Brajesh Kumar Kaushik
Pass transistor logic is a popular alternative to complementary CMOS that aims to reduce the number of transistors required to implement logic by allowing the primary inputs to drive gate terminals as well as source/drain terminals [10]. This is different from logic families that we have studied so far, which only allows primary inputs to drive the gate terminals of metal oxide semiconductor field-effect transistors (MOSFETs). Figure 4.20 shows an implementation of the AND function constructed that way, using only NMOS transistors. In this gate, if input B is high, the top transistor is turned on and copies input A to the output, When B is low, the bottom pass transistor is turned on and 0 is passed.
3D Double-Gate Junctionless Nanowire Transistor-Based Pass Transistor Logic Circuits for Digital Applications
Published in IETE Journal of Research, 2022
Achinta Baidya, Trupti R. Lenka, Srimanta Baishya
The main advantage of the pass transistor logic circuit is reduction in the number of transistors compared to conventional CMOS circuits. Pass transistor logic-based AND gate in Figure 6 uses only two n-JNTs. Transistor number decreases by 50% compared to CMOS configuration. Again Pass transistor logic circuits have an advantage of very low power dissipation as its operation depends only on the input signal voltages and no separate power supply is required. Two-input n-JNT PTL schematics for AND and OR gates, along with truth tables, are shown in Figures 6 and 7. These PTL circuits are prepared using only n-type JNTs. Keeping the gate voltages fixed, if we invert the inputs, PTL AND gate can work as an NAND gate and OR gate can work as an NOR gate. Thus, evaluating PTL AND and OR gate performance of JNT we can predict performance in NAND and NOR too.