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Logic Circuits and Standard Cells
Published in Christian Piguet, Low-Power CMOS Circuits, 2018
A transmission gate, controlled by an input variable, connects another input variable to the gate output. This means that some inputs are connected to transistor sources and not only to the gates of transistors. Compared to the branch-based style, for which sources of transistors or branches are always connected to Vss {0} or to Vdd {1}, in transmission gate designs, sources of transistors or branches can also be connected to input variables. Thus, some cubes in the Karnaugh map are not only “0” cubes indicated by {0} or “1” cubes by {1}, but also some cubes identified by {input}. The content of the cubes is not “0” or “1,” but is identical to a given input variable (or the complemented input). As a result, some cubes containing both “0” and “1” can be chosen, provided that the arrangement of “0” and “1” are identical to a given input.
CMOS Circuits
Published in Vojin G. Oklobdzija, Digital Design and Fabrication, 2017
Eugene John, Shunzo Yamashita, Dejan Marković, Yuichi Kado
The transmission gate can be used to realize logic gates and functions. Consider the exclusive-OR (XOR) gate shown in Fig. 2.14 [5]. When both inputs A and B are low, the top TG is ON (and the bottom TG is OFF) and its output is connected to A, which is low (logic 0). If both the inputs are high, the bottom TG is ON (and the top TG is OFF), and its output is connected to A′, which is also a low (logic 0). If A is high and B is low, the top TG is on and the output is connected to A, which is a high (logic 1). Similarly, if A is low and B is high, the bottom TG is on and the output gets connected to A′, which is a high (logic 1), which is the expected result of a XOR gate. In Fig. 2.14, if we change B to B′ and B′ to B, the circuit will realize the exclusive-NOR (XNOR) function. In the next section we will use transmission gates to realize latches and flip-flops.
10T FinFET based SRAM cell with improved stability for low power applications
Published in International Journal of Electronics, 2022
Figure 3 represents the FinFET based 10 T SRAM cell. The cell consists of 5 transistors to form inverter pair, 1 access transistor, and a transmission gate. The transmission gate is nothing but the parallel connection of one NMOS and PMOS transistor (Sharma & Birla, 2021). Hold operation is taking place when all the signals are set to zero except the three signals, which form the simple connection of the inverter pair. Data can be read through the right portion of the cell with the help of M9 and M10 transistors. Write operation is taking place through a left portion of the cell by using bit line BL. Transmission gate should be in ON condition in all the three operations of the cells so that data can be transferred from one to another end.
Performance Evaluation of Digital Comparator Using Different Logic Styles
Published in IETE Journal of Research, 2018
Dwip Narayan Mukherjee, Saradindu Panda, Bansibadan Maji
The transmission gate logic gives high speed and less power dissipation than conventional CMOS for the reason that of the small transistor stack height, the least number of transistors is required and no complementary input signals are required. The transmission gate comprises of one NMOS and one PMOS transistor, which are associated in parallel. The graphical symbol of the transmission gate appears in Figure 5.
Transmission Gate as Buffer for Carbon-Nanotube-Based VLSI Interconnects
Published in IETE Journal of Research, 2018
A transmission gate (Figure 1(a)), or analogue switch, is defined as an electronic element that selectively blocks or passes a signal level from the input to the output. Also, it is known that an nFET and pFET cannot pass a strong logic 1 and logic 0 voltages, respectively [1]. So, by connecting the two devices in parallel, the full voltage range from 0 V to VDD can be transmitted.