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Introduction to Mechatronic Systems
Published in Bogdan M. Wilamowski, J. David Irwin, Control and Mechatronics, 2018
The arithmetic logic circuit is composed of a group logic gate that performs a Boolean logical operation on a set of meaningful logic inputs and produces a set of corresponding logic outputs. Logic gates are primarily implemented electronically using diodes or transistors, and a logic level is represented by a voltage or current, which depends on the type of electronic logic in use. A truth table is a table that describes the operational rules of a logic gate and lists the value of the output for every possible combination of the inputs. In order to obtain an efficient implementation, a minimization procedure, some optimizing approach, e.g., Karnaugh maps, the Quine–McCluskey algorithm, or a heuristic algorithm, is used to reduce the circuit complexity.
Analogue–digital conversion
Published in David Crecraft, David Gorham, electronics, 2018
To begin with let us see how we can generate a voltage that corresponds to a binary codeword using the circuit shown in Fig. 7.3. The circuit comprises a 4-bit register which stores the binary codeword, and a resistor network. The voltage level at an output of the register will depend upon whether a 0 or a 1 is stored in that bit position. For convenience assume that the voltage levels are 0 V and 5 V for a 0 and a 1 logic level, respectively. Also assume that the values of R1 to R4 are R1=R, R2 = 2R, R3 = 4R and R4 = 8R. This is called a binary-weighted resistor network.
Logic Gates
Published in John C. Morris, Digital Electronics, 2013
In TTL circuits the logic level ‘0’ could be considered as 0 V while logic level ‘1’ would be defined as +5 V. However there are practical factors which must be considered. To expect voltage levels to be exact is unrealistic, zero volts may actually be ‘almost zero’, i.e. 0.2 V, while +5 V may in reality be 4.6 V. If the equipment is designed to switch on the specific levels of 0 V and +5 V, operational problems will be caused. Noise will often be present in most systems and this may appear on the pulse waveform as shown in Fig. 2.2. If the equipment ‘sees’ everything above 0 V as ‘1’ and everything below +5 V as ‘0’ the noise present on a single pulse may well appear as many pulses.
A 40-nm low-power WiFi SoC with clock gating and power management strategy
Published in International Journal of Electronics, 2023
Han Su, Jianbin Liu, Yanfeng Jiang
The chip with integrated multi-stage power management unit (PMU) supports several low power modes to provide the lowest leakage and optimised dynamic power consumption. The diagram of the PMU is shown in Figure 2. The power control unit (PCU) consists of logic circuit to accomplish logical judgements of external signals and excitations through operators, comparators or amplifiers, and then feeds them into a low dropout regulator (LDO) to realise power management. The LDO illustrated in Figure 2 includes an error amplifier, a pass transistor, a feedback network and loads to regulate an output voltage that is powered from a higher voltage for different modules of the SoC (Day, 2002; Ramakrishna, 2014). The PMU also has a DC-DC converter which is a switching regulator with higher power conversion efficiency and multiple outputs (Wu & Chen, 1998). By controlling the voltages fed to each voltage domain, the clock gating can be accomplished and low power modes transformation can be realised. For the control signal from the CPU is not the same voltage as PCU, a voltage transfer circuit is used to transmit the logic level DVCC to VDD, as shown in Figure 3. The design can avoid the influence of the indeterminate state under the Shutdown mode, owing to the power of CPU is cut off. When EN is disabled, the input is fixed at low level and the output at high level.
A 0.7 pJ/bit, 1.5 Gbps Energy-Efficient Image-Based True Random Number Generator
Published in IETE Journal of Research, 2023
Dhirendra Kumar, Lakshmi Likhitha Mankali, Prasanna Kumar Misra, Manish Goswami
Figure 1 shows the basic building block diagram of the proposed TRNG. The block diagram consists of source selection logic, hashing block (HTB), event counting circuit (ECC) and a multiplexer (MUX). Lava lamp, LASER, LED, webcam are some sources used for the generation of different images, selected from meta-stable control line feeder MUX. Meta-stability shows the caliber of a digital electronic system to prevail in a meta-stable or an unstable equilibrium state timelessly [13,14]. In this unstable equilibrium state, the circuit is inadequate to go into a stable “1” or “0” logic level. The proposed design uses a meta-stable block that consists of a cross-coupled inverter connected in the feedback path (Refer Figure 2). The obtained images of fixed pixel size were resized and compressed before converting the colored image to gray image in the HTB block. The difference hashing algorithm was also applied to compute the difference between the adjacent pixels to give output (rand1) as either logic low or high to later act as random clock. Hence for N available pixels, the output from the hashing block is N-1 bits. This output is further logic ANDed with an external clock (clk) to completely act as random clock (clock) for event counting circuit (ECC) comprising of LFSR and pass transistor, which, when passed through a MUX (control line selected again through a meta-stable block for increased randomness), generates true random numbers at output (RAND_OUT).
Performance Evaluation of Digital Comparator Using Different Logic Styles
Published in IETE Journal of Research, 2018
Dwip Narayan Mukherjee, Saradindu Panda, Bansibadan Maji
In the event that the voltage of a low logic level is applied to the input, subsequently, PMOS is in ON condition and give a low impedance path from the output. In this way, the output goes to a high level of . If the voltage of a high logic level is connected to the input, and at that time NMOS is in ON condition and give a low impedance path from the ground to the output. Hence, the output goes to a low logic level of 0 V. The substrate of NMOS is always connected to the ground while the substrate of PMOS always connects to . CMOS logic style is really an extension of CMOS inverters to multiple inputs [8]. The two-bit digital comparator using the CMOS logic technique is shown in Figure 4.