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Novel Subthreshold Modeling of FinFET-Based Energy-Effective Circuit Designs
Published in Balwinder Raj, Ashish Raman, Nanoscale Semiconductors, 2023
Kavita Khare, Ajay Kumar Dadoria, Afreen Khursheed
However, further delving into the issue of power dissipation; it can be stated that totality power utilization in a circuit is mainly due to three key reasons, that is, dynamic-power consumption, short-circuit-power consumption and static or leakage power consumption. Two type of scaling is most popular in VLSI circuits technology constant field scaling and constant voltage scaling. Power supply holds a direct proportionality to dynamic power consumption, so reducing power significantly improves the overall performance of circuit. Scaling the supply of power in IC is for the most widely adopted scheme for reducing the dynamic and short-circuit power utilization, at the trade-off of a hike in propagation delay [4] due to lesser transistor current and by diminishing clock frequency [5]. Due to this supply, the voltage of the critical path is not altered because of speed constrain of the design. To rule out this problem, it is advised to use multivalued-VDD system; in this scenario, the critical path is dispensed with regular power supply (VDDH), and the noncritical trail is dispensed by the downscale of supply voltage (VDDL) [6]. This creates diverse voltage levels [7], and to facilitate the communication among each other, a voltage-level converter, termed a level shifter (LS), is employed as an interface between the circuit in a low-power circuit design.
Low-Power Techniques for Network-on-Chip
Published in Santanu Kundu, Santanu Chattopadhyay, Network-on-Chip, 2018
Santanu Kundu, Santanu Chattopadhyay
Yuan and Cheng (2005) proposed an improved circuit as shown in Figure 6.7 to reduce the contention problem so as to achieve high-speed and low-power consumption. In this circuit, the level shifter circuit converts a signal X on the lower supply voltage side into a signal Y on the higher supply voltage side. The signal X¯ is transmitted to the gates of transistors MN3 (MN3 is the NMOS transistor of inverter as shown in Figures 6.6 and 6.7), MN6, and MP6. A signal x for the inverted phase, which is generated by an inverter constituted by transistors MP1 and MN1, is transmitted to the gates of transistors MN2, MN5, and MP5. The respective gates of transistors MP2 and MP3 are cross-connected to the drains of transistors MP3 and MP2, whereas the sources of both transistors are connected to the higher supply voltage VDDH. A node B is connected to an output buffer circuit, constituted by transistors MP4 and MN4, which is connected to the higher supply voltage VDDH.
CMOS Amplifiers
Published in Tertulien Ndjountche, CMOS Analog Integrated Circuits, 2017
Operational transconductance amplifiers, which are equivalent to a voltagecontrolled current source, are generally based on single-stage structures, while additional gain stages and an output buffer are required for the design of operational amplifiers operating as a voltage-controlled voltage source. A highperformance operational amplifier should provide a high input impedance, a high open-loop gain, a large CMRR, a low dc offset voltage, a low noise, and a low output impedance. Figure 5.12 shows the block diagram and symbol of a single-ended operational amplifier. The output of the differential stage is supplied to additional gain stages in order to meet the high gain requirement. A level shifter is needed whenever the dc voltage difference introduced between the input and output voltages of a stage should be canceled. An output buffer with unity gain will be necessary if the amplifier is supposed to drive a resistive load. The use of a compensation network is necessary to avoid the conditions leading to instability when the amplifier operates with a feedback.
An Overview on MOSFET Drivers and Converter Applications
Published in Electric Power Components and Systems, 2021
Mustafa Ergin Şahin, Frede Blaabjerg
The invention of Parks provides a resonant switching for a FET and associated circuits such as power supplies with synchronous output rectifiers. The resonant switching for a JFET starts a bipolar mode operation with a diode clamping of the gate, which efficiently uses bipolar mode operation without a separate bias power supply [59]. A new gate driver apparatus is invented as an energy recovery circuit. These apparatus use a first loop circuit to discharge the energy from the gate capacitor to an inductor when the gate driver is turned off and use a second loop circuit to release the energy from the inductor to the power supply when the gate driver is turned on [60]. A matching circuit for coupling a MOSFET driver to the gate of an enhancement mode JFET is optimized for driving a MOSFET in this invention [61]. A complicated high-speed MOSFET output driver is invented at the low voltage and high voltage sides. This driver includes a voltage level shifter stage that changes an input signal at a first voltage level to an output signal at a second voltage level [62]. A circuit package providing isolation between a controller on the primary and secondary sides of a switched power supply is invented [63]. The other invention describes a system architecture of dynamic MOSFET gate driver and control scheme is adjust both the turn-on and the turn off resistance of gate driver within a single switching cycle, reduce the electromagnetic interference in the system and, minimize the conduction loss of a power MOSFET during operation [64].