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Robustness of Digital Circuits at Lower Voltages
Published in Christian Piguet, Low-Power CMOS Circuits, 2018
NBTI is a result of a negative bias applied to the gate of a p-channel MOS transistor with respect to the bulk. The mechanism is temperature activated. NBTI results in the degradation of many transistor parameters (drive current, trans-conductance, and threshold voltage), but the threshold voltage appears to be the most degrading one. NBTI was first reported in 1967, but the attention devoted to this mechanism has been escalating over the last couple of years, due to the introduction of gate-oxide nitridation [13] that enhances NBTI and the fact that other oxide wear-out mechanisms, such as HCE and oxide breakdown, were expected to become less severe as the gate oxide scales down. NBTI is strongly process dependent. It has been reported that a higher nitrogen concentration in the oxide [13], boron penetration [14], and plasma processing can enhance NBTI, while fluorine incorporation in the gate dielectric is beneficial against NBTI [15]. The physical nature of the wear-out mechanism induced by NBTI is not fully understood yet. The most accepted models imply positive charge build-up in the oxideto-bulk and at the Si/SiO2 interface (donor-like interface states) [16,17].
Process Variability and Reliability of Nano-Scale CMOS Analog Circuits
Published in Soumya Pandit, Chittaranjan Mandal, Amit Patra, Nano-Scale CMOS Analog Circuits, 2018
Soumya Pandit, Chittaranjan Mandal, Amit Patra
NBTI refers to the threshold voltage instability in p-channel transistors that is dependent on temperature and transistor geometry, particularly the channel width [112]. NBTI causes an increase in the absolute threshold voltage, degradation of the mobility, drain current, and transconductance of p-channel MOS transistors [126]. This process does not require the presence of a high lateral field and the resulting hot carriers. The mechanism is attributed to the breaking of SiH bonds at the Si-SiO2 interface by a combination of electric field, temperature, and holes, resulting in dangling bonds or interface traps at that interface and positive oxide charge.
Molecular Phenomena in MOSFET Gate Dielectrics and Interfaces
Published in Krzysztof Iniewski, Santosh K. Kurinec, Sumeet Walia, Energy Efficient Computing & Electronics, 2019
S. Arash Sheikholeslam, Hegoi Manzano, Cristian Grecu, Andre Ivanov
Molecular phenomena at the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) channel/dielectric interface are of considerable importance in understanding the kinetics of various degrading mechanisms in transistors. Most of the aging mechanisms impact MOSFETs over time; therefore, designers decrease the clock speed of their chips such that they do not fail during their intended lifetime [1]. This type of techniques is commonly known as guardbanding. Therefore, reliability is a limiting factor to high-speed computation. The main observable effect of aging at transistor level is the shift in threshold voltage. Device scaling is another contributor to the reliability issues. Scaling the MOSFET devices increases the heat density. More heat can accelerate the aging process. The most important aging mechanism are Negative/Positive Bias Temperature Instability (N/PBTI), Hot Carrier Injection (HCI) and Time Dependent Dielectric Breakdown (TDDB). Both NBTI and TDDB have the potential to be studied through classical molecular dynamics due to their nature. NBTI is an interface phenomenon that takes place when a hydrogen atom dissociates from the Si/Oxide interface and diffuses into the oxide due to the electric field caused by the gate potential (Figure 2.1). What remains are the positively charged dangling bonds at the interface [2]. The hydrogen atoms are originally placed at the interface to passivate the Si interfacial dangling bonds, which are known to degrade the threshold voltage. TDDB occurs when the gate dielectric irreversibly breaks down when it is polarized with a high enough electric field such that a conductive path of a few kilo ohms is formed through the dielectric. In case of SiO2, this conductive path will be made of Si.
Design and Simulation of Reliable Low Power CMOS Logic Gates
Published in IETE Journal of Research, 2023
Temporal degradation impacts the reliability of CMOS circuits in DSM regime. Temporal degradation behaviour is checked for the proposed approach and compared with the existing techniques. Bias temperature instability (BTI) is dominant reliability concern if oxide thickness is less than 2 nm [16]. Negative bias temperature instability (NBTI) effect is considered for temporal degradation for ring oscillator. NBTI effect occurs in PMOS devices when these are negatively biased. NBTI increases threshold voltage that causes large circuit delay than the design specification which causes timing violation and logic failure [17]. Figure 14 shows the NBTI effect on ring oscillator circuit for different methods at 22 nm technology node. There are a number of PMOS devices in a circuit and these are impacted by the NBTI effect differently. Figure 14 depicts the NBTI effect for the PMOS device whose source terminal is connected to power supply in pull-up network in the last stage of the ring oscillator. A small change in threshold voltage (delvth0) is calculated for all the methods for 5 years.
Optimisation of SRAM cell in 7-nm node by response surface method
Published in International Journal of Electronics, 2022
Ding Yan-Yan, Guangjun Zhang, Yanfeng Jiang
The stability of the SRAM cell shows a negative temperature tendency because of the effect of Negative Bias Temperature Instability (NBTI), as shown in Figure 12(a). The NBTI effect refers to the fact of the p-MOSFET performance degradation when a negative bias voltage is applied to the gate under high temperature conditions (Huard et al., 2006). The performance degradation mainly includes the increment of the gate current, the decline of the threshold voltage, the decrement of the sub-threshold slope. Actually, the NBTI effect is also affected by temperature conversely (Singh & Mahmoodi, 2010).
Simple and fast simulation approach to investigate the NBTI effect on suspended gate MOS devices
Published in International Journal of Electronics Letters, 2020
Cherifa Tahanout, Hakim Tahi, Bouchera Nadji, Lotfi Hocini
Despite many advantages of SG-MOS devices, their large-scale exploitation has been thwarted by a number of reliability issues such as stiction (Hoang, Wu, Golinval, Arnst, & Noels, 2018; Melle et al., 2007; Tanner et al., 2000), mechanical fatigue (Allameh et al., 2003), creep (Oha & Sharpe, 2004), and dielectric charging (van Spengen, 2012). In addition, the reliability features of standard CMOS technology could affect the lifetime of SG-MOS devices, such as negative bias temperature instability (NBTI) (Jain, Islam, & Alam, 2010; Stathis, Mahapatra, & Grasser, 2018), and gate dielectric breakdown (TDDB, time-dependent dielectric breakdown) (Jain, Palit, et al., 2012). Indeed, the continuous MOS device shrinking has accelerated the reduction of the gate oxide thickness from the technology node to another (with no reduction of the operating voltage compared to more aggressive devices scaling). Consequently, the gate oxide electric field increased, and the devices working temperature augmented, due to the high power density, caused by the high number of transistors per area. Therefore, during the operation of the MOS device under these conditions (high gate electric field and high devices working temperature), the carriers of inversion layer could react with defects precursors (example: breaking of the Si3≡ Si-H and/or O3≡ Si-Si ≡O3 bonds), as a result, the interface (∆Nit) and oxide (∆Not) tarps are induced (Grasser et al., 2009). Thus, the intrinsic feature mechanisms of MOS devices are accelerated. It is well known that the NBTI degradation is a crucial reliability concern for modern CMOS technology, and this degradation arises from generation ΔNit and ΔNot (Grasser et al., 2009; Schroder & Babcock, 2003). In the case of conventional PMOSFET, both interface-traps and oxide-traps are positively charged, leading to negative threshold voltage shifts (∆Vth), consequently the drain current decreases. In addition, the inversion carriers (holes) mobility could be affected by the generated traps charge (∆Nit and ∆Not), thus the transconductance (gm) might be affected (decreases). Therefore, the circuit performances and lifetime are affected (Schroder & Babcock, 2003). Since the interesting advantages of SG-MOS devices are the possibility of its co-integrated on the same chips with the associated electronic circuits using the standard CMOS technology, it is worth to study the effect of NBTI degradation on the lifetime of SG-MOS devices. We should note that there are very few works that investigated the NBTI degradation on SG-MOS devices (Jain, Islam, et al., 2010, 2012). In these works, the authors have used a general theoretical framework of interface traps induced by NBTI degradation (using a Reaction-Diffusion or R-D Model (Islam, Kufluoglu, Varghese, Mahapatra, & Alam, 2007)) to study the consequence of high oxide field in SG-MOS devices.