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Trends and Challenges in VLSI Fabrication Technology
Published in Balwinder Raj, Ashish Raman, Nanoscale Semiconductors, 2023
Vikas Maheshwari, Neha Gupta, Rashid Mahmood, Sangeeta Jana Mukhopadhyay
Scaling the MOS device size down requires scaling the oxide thickness of the gate dielectric as well. Since 1957, for the manufacturing of the MOS devices, SiO2 has been the preferred material as a gate oxide layer over others. For the latest technology beyond 45 nm, the oxide layer thickness in MOS devices is predicted to be less than 0.5 nm, which is nearly equivalent to a few atomic layers of SiO2. Therefore, the next challenging issue is related to the rapid scaling of the dielectric thickness used to provide isolation between the gate and the bulk semiconductor. For an oxide layer thickness less than 0.4 nm, direct tunneling becomes a serious problem, and the problem increases with a decrease in the oxide thickness, where the gate leakage current increases exponentially with a decrease in the dielectric layer thickness. These tunneling currents result in a direct impact on the static power consumption and provide a limiting scenario for the further shrinking of the physical thickness of the oxide dielectric layer. For low-static power consumption, less tunneling current is tolerable, but on the other hand, a thicker dielectric layer is necessary for achieving the required performance of the device.
Carbon Nanotube Electronics
Published in Ann Rose Abraham, Soney C. George, A. K. Haghi, Carbon Nanotubes, 2023
A potential barrier exists at every contact between metal and semiconductor. This is known as the Schottky barrier. In this device, source and drain terminals are metals and the terminal contact between metal and nanotube has a Schottky barrier. Working principle is based on direct tunneling through this barrier at source–channel junction. Transconductance is gate voltage-dependent as the barrier width is controlled by this voltage. With increase in gate bias, barrier width decreases which further increase in quantum mechanical tunneling and current flow in the transistor channel. Occurrence of ambipolar conduction at low gate oxide thickness is a major setback. This can lead to exponential increase in leakage current. Increase in gate oxide thickness reduces the leakage current as well as improves the performance. Asymmetric gate oxide is another alternative solution. Other drawbacks include limited channel length leading to increased source to drain tunneling and inability to place gate and source close by as this leads to increased parasitic capacitance. The schematic diagram of the design is given in Figure 9.8.
Formulation and Classification of Electronic Devices
Published in Michael Olorunfunmi Kolawole, Electronics, 2020
Create a contact window opening in the oxide where to build the transistor’s gate region. Deposit on the interlayer insulation film by sputtering. Sputtering is the process of covering a surface with metal. Aluminum is the standard “wire” for ICs and is usually deposited by “sputtering.” When a Physical Vapor Deposition (PVD) process deposits polysilicon, the process is often known as “sputtering.” Tungsten (grown from a gas reaction) is sometimes used, with increasing interest in copper. Note that the gate is a conductive layer, which is separated from the bulk silicon by a thin gate oxide. The gate oxide needs to be thin since the electrical field must transfer across this insulator. The thinner the metal oxide layer, the faster and more energy efficient the electronic component is. After metallization is complete, the surface is covered with another interlayer insulation film (or the “cover layer”) for protection, and the wafer is now complete.
Design of energy efficient domino logic circuit using lector technique
Published in International Journal of Electronics, 2022
Km Anjali Verma, Manish Kumar, Saurabh Kumar, R. K. Chauhan
This manuscript represents a modification in the existing technique of foot-driven stack transistor. The Lector technique (Hanchate & Ranganathan, 2004) and an NMOS transistor are used in the modified circuit, which is driven by a dynamic node. The major source of power consumption in digital circuits is leakage current, short circuit current, and charging-discharging of load capacitance. The major reason for leakage is subthreshold leakage and gate oxide leakage. The proposed lector-based domino logic circuit can effectively be used to reduce gate oxide and subthreshold leakage current. Therefore, the proposed circuit can be used for battery-powered applications and can also be used for wide fan-in circuits (Gupta & Khare, 2013). The modified domino circuits have low power dissipation, delay, high noise margin, and better power delay product.
A 4:1 Multiplexer using dual chirality CNTFET-based domino logic in nano-scale technology
Published in International Journal of Electronics, 2020
Sandeep Garg, Tarun K. Gupta, Amit K. Pandey
Dynamic CMOS logic circuit represents lower threshold voltage, logical effort and parasitic capacitance compared to static CMOS logic circuits. Therefore, dynamic circuits operate faster and occupy lesser area on chip in contrast to static circuits. For implementing large Fan-in gates, dynamic logic is preferred over static logic in high-speed digital applications. The transistor count on chip is increasing due to technology scaling. This increase in chip density causes more number of interconnects on the chip that increases the capacitive coupling between the interconnects. This coupling causes crosstalk between the interconnects due to noise pulses and reduces the speed of the domino circuit. The supply voltage (VDD) is scaled down for reduction in power consumption of domino circuits. Threshold voltage (Vth) of the transistors is reduced along with the decrease in supply voltage to maintain the power and delay performance of transistors. This increases the sub-threshold current that will make the circuit faster and reduces noise immunity. In addition, due to technology scaling, the thickness of gate oxide decreases which increases gate leakage current. Therefore, at high frequencies, the performance of domino logic is degraded due to leakage current, low Vth and noise sources (Anis, Areibi, & Elmasry, 2003; Dadashi, Mirmotahari, & Berg, 2016; Roy, Mukhopadhyay, & Mahmoodi, 2003).
Performance Study for Vertically Quad Gate Oxide Stacked Junction-less Nano-sheet
Published in IETE Journal of Research, 2023
M. Prasad, U. B. Mahadevaswamy
Finally, the triple-fin quad gate vertically staked junction-less Nano-sheet NMOS device is modified by added with HfO2 for gate oxide stack with 1nm thickness and SiO2 is 1nm thickness, respectively. The approximate total gate oxide thickness is about 1.156nm, Which is simulated at a drain voltage of 0.1V and 1V, respectively and the gate voltage is varied from 0V to 1.2V with work function 5.1. The result shows the notable improvement in increased Ion and minimized Ioff with Ion/Ioff ratio is 3 times higher than in linear region and 1.637 times higher than in saturation compared to triple-fin quad gate vertically stacked junction-less Nano-sheet. The 3D view of gate oxide stacking Nonosheet as shown in Figure 1 and results are plotted as shown in Figure 5.