China
Africa
Explore chapters and articles related to this topic
Bottom-Up Approaches for CMOS Scaling in the Nanoscale Era
Published in James E. Morris, Krzysztof Iniewski, Nanoelectronic Device Applications Handbook, 2017
Mrunal A. Khaderbad, V. Ramgopal Rao
Miniaturization of CMOS devices has major advantages like increased processing power, higher transistor density, and reduced cost per transistor. But, the scaling also leads to short-channel effects (SCEs) like increased leakage currents, hot-carrier injections, and increased source–drain resistance [31,32]. Besides SCEs, in the nano-CMOS regime, there are challenges in the back-end-of-line (BEOL) processes such as increased line resistance. Though low-k dielectrics enable interconnect scaling, they pose leakage and reliability problems [33,34]. Coming to front-end-of-line (FEOL), for the 45 nm node and beyond, high-k/metal-gate technologies have been explored to reduce leakage currents and reliable high-speed operation [35]. For this, high-k materials, including hafnium oxide (HfO2) and Al2O3, are investigated to replace the silicon dioxide gate dielectric. Concurrently, mid-gap metals and dual work function metals are suggested to eliminate effects such as poly-silicon depletion and poly-silicon dopant penetration. To achieve acceptable threshold voltage (Vt), gate electrodes must have appropriate work functions. In this scenario, metal gate work function tuning is an important process step to optimize device performance in nanoscale technologies.
Sensitivity of SET Pulse-Width and Propagation to Radiation Track Parameters in CMOS Inverter Chain
Published in IETE Journal of Research, 2022
The 3-D mixed-mode simulations of CMOS inverter and inverter chain are carried out using Sentaurus TCAD [15]. The device parameters of bulk NMOS are : gate length is 45 nm, gate oxide thickness is 2 nm, source/drain doping is cm n-type with Gaussian doping profile, substrate doping is cmp-type with constant doping profile and metal gate work function is 4.19 eV. The device parameters of SOI-NMOS are: gate length is 45 nm, gate oxide thickness is 2 nm, silicon thickness is 10 nm (fully depleted), buried oxide thickness is 30 nm, source/drain doping is cm n-type with Gaussian doping profile, channel/body doping is cmp-type constant profile, doping of the substrate (acts as ground plane) is cmp-type with constant doping profile, and metal gate work function is 4.7 eV. The two devices are calibrated using 45 nm predictive technology model (PTM) low power SPICE model card [16]. The power supply voltage (V) used is 1.1 V.
Integral impact of PVT variation with NBTI degradation on dynamic and static SRAM performance metrics
Published in International Journal of Electronics, 2022
Siona Menezes Picardo, Jani Babu Shaik, Nilesh Goel, Sonal Singhal
The simulation procedure to determine performance metrics of SRAM cell under the impact of PVT and NBTI degradation is shown in Figure 3. The circuit design and SPICE simulations are performed in the CADENCE Virtuoso platform. The technology library considered are from modern planar 45 nm high-k metal gate (HKMG) CMOS technology. The shift in threshold voltage due to NBTI degradation is updated in the technology library is indicated as the ‘NBTI Augmented Technology Library’. The technology libraries (original and NBTI augmented) are used to create 6 T SRAM circuit netlists, i.e. for time-zero and degraded. Cadence SPECTRE is used to perform mean and Monte Carlo (MC) simulations for ‘fresh cases and ‘degraded cases’. The ‘degraded cases’ employ activity factors (‘α’). Supply voltage and temperature are also varied to evaluate the holistic impact on SRAM performance metrics.
Nanowire Transistors: A Next Step for the Low-Power Digital Technology
Published in IETE Journal of Research, 2021
D. Ajitha, K. N. V. S. Vijaya Lakshmi, K. Bhagya Lakshmi
The Nanowire FET proposed with dual material gate and shallow extensions reduces the drain leakages and improves the noise margin suitable for high-frequency microwave applications [100]. In addition to this, the high K dual metal device design is well suitable for high-frequency applications in a variety of analog and digital applications [101]. The Asymmetric gate stack triple metal gate MOSFET (AGSTMGAAFET) has been given a 2D analytical model. This device has excellent drain current, transconductance, output conductance, current gain, and maximum transducer power gain, indicating suitability for various analog applications. Furthermore, the potential and electric field plots obtained have a two-step profile and an extremely low electric field near the drain region, indicating that AGSTMGAAFET has the ability to suppress SCEs [102]. Hence, the different GAA nanowire structures which are designed are the ultimate replacement of conventional devices for future diverse applications and advancements.