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Modeling and Simulation of Emerging Low-Power Devices
Published in Shubham Tayal, Abhishek Kumar Upadhyay, Deepak Kumar, Shiromani Balmukund Rahi, Emerging Low-Power Semiconductor Devices, 2023
M. Venkatesh, G. Lakshmi Priya, S. Arun Samuel, M. Karthigai Pandian
The progressing semiconductor industry has greatly revolutionized human lives. Owing to various geometrical scaling issues in a semiconductor device, researchers are taking efforts to put forth new concepts of gate metal work function engineering. The ON state current is greatly improved by combining two or three distinct materials with various work functions in the gate metal. For several decades, planar bulk transistors have been an integral part of ICs, during which the size of these transistors have steadily decreased. Scaling the device dimensions has reached its physical limit and is on the verge of stagnation in various new technologies. The major limitations include undesirable SCEs, subthreshold leakage current, extreme heat dissipation, and power consumption of the device. To surmount all of these short-channel issues, the best solution can be to increase the electrostatic gate control over the channel. The gate has to be strong in establishing its control over the movement of electrons from source to drain. Therefore, double-, triple-, and surrounding/gate-all-around structures have been proposed to effectively suppress the subthreshold conduction and its corresponding leakage current. In general, having more than one gate can enhance the device characteristics, and such a configuration is called multigate device as shown in Figure 2.11.
High-Mobility Channels
Published in Krzysztof Iniewski, Tomasz Brozek, Krzysztof Iniewski, Micro- and Nanoelectronics, 2017
Only at the 45 nm technology node were the metal gate and high-κ dielectrics, introduced, replacing the traditional poly/SiON gate stack in MOSFETs and allowing further gate dielectric scaling. The next innovation was introduced at 22 nm: the trigate or bulk FinFET. This multigate device architecture has much better gate control and lower SCE and reduces the subthreshold leakage significantly. This is an important innovation as it allows further scaling of the gate pitch and, implicitly, scaling of the LG and VDD. The supply voltage of the transistors had bottomed out at around 1 V, even though dissipated power density had gone up to 100 W/cm2, basically reaching a limit where innovations in packaging and cooling would be needed to guarantee reliable operation of the integrated circuits. A reduced sub-threshold swing and thus lower threshold voltage VT of the FinFET allows the gate overdrive to be kept constant while reducing the VDD without compromising the switching speed.
Nanowire Array–Based Gate-All-Around MOSFET for Next-Generation Memory Devices
Published in Suman Lata Tripathi, Sobhit Saxena, Sushanta Kumar Mohapatra, Advanced VLSI Design and Testability Issues, 2020
Krutideepa Bhol, Biswajit Jena, Umakanta Nanda
Several gates on multiple surface surround the channel in case of a multigate device. It thus provides a better electrical control over the channel, allowing more effective suppression of “off-state” leakage current. Multiple gates also allow enhanced current in the “on” state, also known as drive current. Among different multigate devices, cylindrical surrounding-gate MOSFET (metal oxide semiconductor field-effect transistor) provides better gate control over the channel. Also saturated device dimensions produce high gate leakage current and several SCEs such as threshold voltage roll-off, drain-induced barrier lowering, corner effect, and so on. [1,2]. However, many device geometries have already been developed and investigated in detail to improve the performance. Cylindrical gate-all-around (GAA) MOSFET provides superior gate controllability compared with single-gate and other multigate structures [3]. It is considered as one of the better models that has the capability to overcome the physical scaling limit of conventional CMOS (complementary metal oxide semiconductor) technology. The GAA MOSFET in the fully depleted regime shows improved robustness against SCEs and also reduces the threshold voltage and subthreshold swing (SS) [4]. The SCEs in the small-dimension devices result in high off-state leakage current (Ioff) and high SS. So Ion/Ioff ratio of the device decreases significantly, which affects the circuit speed and dissipation power. However, the impact of SCEs can be reduced by scaling the gate oxide thickness and increasing the channel doping concentration for channel length beyond 100 nm [5].
Analysis of 14nm technology node In0.53Ga0.47As nFinFET integrated with In0.52Al0.48As cap layer for high-speed circuits
Published in International Journal of Electronics, 2019
The cross-sectional view of 14 nm channel length InGaAs nFinFET device is shown in Figure 1. The 3D TCAD Synopsys tool is used to design and simulate the device. The parameters for designing the device are adopted from ITRS 2013 (ITRS, 2013). The parameters like gate length, oxide thickness, body thickness and channel doping are adopted from the high-performance logic multigate device for III–V semiconductors. CMOS compatible structural process of self-aligned InGaAs nFinFET is considered for designing the device (Djara et al., 2016). InGaAs is deposited on BOX (Burried Oxide) of thickness 37 nm, with silicon substrate. The nitride spacer (k = 7.5) has been used across the vacant region in the device. The other dimensions and parameters are mentioned in Table 1.