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Electrothermal Modeling of Substrates
Published in Yue Ma, Christian Gontrand, Power, Thermal, Noise, and Signal Integrity Issues on Substrate/Interconnects Entanglement, 2019
The microelectronics sector is facing many challenges to produce smaller and more powerful computing chips. Thermal management is one of those, which comes from new developments such as chip stacking (3D chips) and increasing the computing power. In addition to increased cooling needs, the mobile device market tends to reduce the space available for heat dissipation. In this context, conventional air heat sinks are no longer adequate and alternative compact and high-heat flux cooling approaches are required. Micro-heat pipe cooling with porous medium is an approach that offers both compactness and cooling performance that can be well above air cooling.
Introduction to Mechatronic Systems
Published in Bogdan M. Wilamowski, J. David Irwin, Control and Mechatronics, 2018
For over half a century, the technology of microelectronics has been advancing through miniaturization, leading to significant increases in computing power and continuous decreases in manufacturing cost. Microelectronics is a subfield of electronic engineering. Microelectronics is the subject of the study and manufacture of electronic components that are usually small scale and are made from semiconductors.
Multifunctional Structures and Materials
Published in Yoseph Bar-Cohen, Advances in Manufacturing and Processing of Materials and Structures, 2018
As mentioned previously, multifunctional structures are currently realized by combining functionalities made from disparate materials using disparate serial manufacturing processes. For example, consider a notional electronics integration into a composite structure. First, microelectronics chips are manufactured in a microelectronics foundry, packaged on a separate line, and then potentially attached to a circuit board along with other circuit elements in yet a different assembly line. Next, in another completely separate composite fabrication process, the circuit board, along with connective wiring, is laid up within plies of dry carbon fiber cloth, liquid resin is infiltrated into the layup, and the whole assembly is cured, being sure not to use curing temperatures, which can damage the electronics. The aforementioned collection of “orthogonal” manufacturing process does not seem to match the parallelism found in an ideal multifunctional structure.
Design and Optimization of a Dual-Source Triple Gate FET Using Electrostatically Induced Reconfigurable Property
Published in IETE Technical Review, 2022
Antara Kundu, Priyanka Saha, Subir Kumar Sarkar
For more than 40 years the CMOS technology has followed an incessant scaling following the prescripts of Moore’s law [1]. However, in recent times, this trend has been slowed and is threatened for sub-10 nm because below that quantum tunneling effect arises, which correspondingly distracts the device performance [2]. Thus the microelectronics industry is researching for new alternate device structures to enable continued device miniaturization. Researchers have proposed several substitutes to traditional MOS to overcome the portents of associated short channel effects (SCEs) [3,4]. Gate work function engineering, lateral channel engineering, multi-gate geometry, hetero dielectric-based Silicon On Insulator /Silicon On Nothing (SOI/SON) FET, and Tunneling FETs are some of the emerging contenders that have shown admirable performance compared to short-channel MOSFET. Reconfigurable FETs (RFETs) are another interesting option to reduce the number of devices in the future circuit because of their reprogrammable operation. The unique feature of switching from MOSFET to TFET and vice versa with the application of appropriate gate voltage makes it highly preferable in the device research community [5,6] with a possible choice to replace fin-shaped FETs, SOI/SON [7], and other planner devices for future-generation VLSI circuits. By allowing the same device to behave as MOSFET and TFET, such RFET devices facilitate the implementation of multiple functionalities with a single device rather than reducing the size of the transistor itself, a substitution to the classic trend of downscaling [8,9].
Evolution of Rutherford’s ion beam science to applied research activities at GNS Science
Published in Journal of the Royal Society of New Zealand, 2021
John V. Kennedy, William Joseph Trompetter, Peter P. Murmu, Jerome Leveneur, Prasanth Gupta, Holger Fiedler, Fang Fang, John Futter, Chris Purcell
While we have continued research in materials for advanced sensors, microelectronics and communication technologies, as well as our environmental research, our research’s main focus has recently shifted towards developing new materials for energy efficiency and to support New Zealand’s transition to a low carbon future. Some recent examples are given below: Microelectronics, sensors and communication technologies Communication 5GQuantum computingMagnetic semiconductors for spintronic and magnetic sensor applicationsMaterials for low carbon future CatalystsThermoelectric materialsEnergy efficiency – low friction coatingsNZ magnetic minerals for inroad charging systemsEnvironmental research (air and water)
Design Automation and Testing of MEDA-Based Digital Microfluidic Biochips: A Brief Survey
Published in IETE Journal of Research, 2020
Pampa Howladar, Pranab Roy, Hafizur Rahaman
However, certain limitations were oblivious in the current designs of DMFBs. These can be summed up in short as (i) specific limitations in the droplet size as it may restrict possible resizing in droplet volumes in a fine-grained way (ii) sensors are less integrated into real-time detection (iii) special fabrication process and the related reliability are essential. Concurrent and executions of multiple bioassays in a DMFB 2 D array requiring complex system integration as well as resource management are expected to result in an increase in design complexity to a large extent [7]. In addition to this, the integration of microelectronics with biochip technology is anticipated to grow fairly rapidly in the future. For example, a commercial chip embedded with 600,000 electrodes has been announced recently. This is based on one-to-one mapping concept (referred to as direct-addressing pin assignment) between electrodes and control pins. Implementing this concept on DMFBs may lead to high production cost, low reliability, problems in routing of interconnects as well as high fabrication cost [8]. Moreover, an increase in the number of control pins may result in an increase in the number of PCB layers.