Explore chapters and articles related to this topic
Paradigm Shift of On-Chip Interconnects from Electrical to Optical
Published in Thomas Noulis, Noise Coupling in System-on-Chip, 2018
Swati Joshi, Amit Kumar, Brajesh Kumar Kaushik
As the technology advances, interconnects are limiting the performance of high-speed systems. This has encouraged researcher to explore alternative interconnect materials and technologies that can replace existing conventional copper interconnect technology with less power consumption, better performance, cost effectivity, and compatibility with existing CMOS fabrication processes. Graphene, a two-dimensional allotrope of Carbon atoms, with its unique optical properties, is emerging as a promising substitute for prevalent optoelectronic, plasmonic, and nanophotonic materials [85]. It is compatible with standard CMOS processes and could be integrated with other grown technologies for high-data-rate (inter and intra-chip) optical blocks. It has tunable optical properties which can be controlled via doping or application of voltage. Due to its large thermal conductivity, high mobility, and large charge-carrier concentrations, it is considered a suitable candidate for electro-optic devices such as modulators or photodetectors [86, 87]. Several kinds of research have shown that graphene-based on-chip optical devices could meet the desired performance requirement for high-speed systems and chips.
k Integration
Published in Robert Doering, Yoshio Nishi, Handbook of Semiconductor Manufacturing Technology, 2017
Girish A. Dixit, Robert H. Havemann
Over the past decade, integrated circuit scaling and performance needs have driven significant changes in interconnect materials and processes at each successive technology generation. Foremost among these changes has been the transition from aluminum to copper conductors [1-7]—a transition that is virtually complete for logic devices and now underway for memory devices [8,9]. The primary impetus for this ongoing transition has been a need for the improved performance afforded by copper’s lower resistivity as compared with aluminum as well as by copper’s ability to accommodate higher current densities. The need for improved performance has also driven a concomitant change in the insulator surrounding the conductor, which for logic devices has transitioned from the traditional silicon dioxide dielectric to materials with lower dielectric constant (low-k), such as F-doped oxides and C-doped oxides. The simultaneous integration of copper with low-k dielectrics presented a significant challenge to the industry, and, while the manufacturing use of copper interconnects has become pervasive, each successive technology generation offers new challenges in terms of meeting density, performance, and reliability requirements. This chapter will provide an overview of copper and low-k interconnect integration including process architectures, materials, performance, and reliability issues as well as future scaling challenges and potential technology directions.
Inductance Effects in Global Nets
Published in Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar, Handbook of Algorithms for Physical Design Automation, 2008
On-chip inductance has currently become more important with faster on-chip rise times and wider wires. Wide wires are frequently encountered in clock distribution networks and in upper metal layers. These wires are low-resistance lines that can exhibit significant inductive effects. Furthermore, performance requirements are pushing the introduction of new materials such as copper interconnect for low-resistance interconnect and new dielectrics to reduce the interconnect capacitance. These technological advances increase the importance of inductance.
Performance and Power Optimization for Intercalation Doped Multilayer Graphene Nanoribbon Interconnects
Published in IETE Journal of Research, 2022
Bhawana Kumari, Manodipan Sahoo
The IC industry has shifted from transistor-centric to interconnect-centric in recent years because interconnect delay now dominates the transistor delay and is the major factor in determining the total chip delay [1,2]. Copper interconnect has reached its limits because of increase in resistivity, grain boundary scattering effects, degradation in Electro-Migration (EM) reliability leading to reduced current carrying capacity which affects the performance of ICs [3]. Therefore a substitute interconnect material is needed [4]. During the recent past, graphene nanoribbons (GNRs) have rapidly gained importance as an emerging interconnect material [5]. They are exciting prospects for a variety of VLSI circuit applications due to their extraordinary physical properties [6,7]. They have lower resistivity, superior transport properties and higher current carrying capacity than copper in nano-regime [8].
Novel Subthreshold Modelling of Advanced On-Chip Graphene Interconnect Using Numerical Method Analysis
Published in IETE Journal of Research, 2021
Nikita R. Patel, Yash Agrawal, Rutu Parekh
The technology node used is 22 nm for the performance analysis of different interconnects materials. The channel width of NMOS and PMOS transistors considered is 1 μm and 2 μm respectively [21–22]. The interconnect physical dimensions are as per international technology roadmap for semiconductors (ITRS) [28]. The interconnect parasitics viz. per unit length resistance, inductance and capacitance for copper interconnect are 61.9 KΩ/m, 2 nH/m and 120 fF/m respectively. These values for MLGNR interconnect are 2.72 KΩ/m, 7 nH/m and 44 fF/m respectively.