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Clock signal and its attribute for agriculture
Published in Govind Singh Patel, Amrita Rai, Nripendra Narayan Das, R. P. Singh, Smart Agriculture, 2021
Different kinds of delays found within the circuit: Propagation delay: It is defined as the time required by the signal to flow from the input terminal to the output terminal of a logic gate. Most frequently it is defined as a rising–falling waveform applied to a block; maximum time is taken from rising input/rising 50% mark to the output rising/falling 50% mark.Gate delay: The maximum time required by a logic gate to compute the expected output. Time taken on receiving an input for generating the expected output is termed as gate delay. For nanometer design, its values are in the unit of nanoseconds with precision picoseconds.Contamination delay: It is the minimum time required from the input 50% threshold to the output 50% threshold. Contamination delay follows the minimum delay along the circuit, that is, it provides the shortest path.Transmission delay: It is the delay that arises due to the data being transmitted which is not dependent on the input or output nodes.
Tunnel FET: Working, Structure, and Modeling
Published in Niladri Pratap Maity, Reshmi Maity, Srimanta Baishya, High-K Gate Dielectric Materials, 2020
where F is the frequency at which the inverter is switched on, C is the total gate capacitance, and VDD is the power supply. The frequency is related with propagation delay, lower the propagation delay higher is the frequency at which the circuit can be operated, of course, with higher power dissipations as well. A figure of merit or a quality measure of the particular circuit technology is power delay product (PDP), given by PDP=PD(tPHL+tPHLH)
Processor Physics and Moore’s Law
Published in Vivek Kale, Parallel Computing Architectures and APIs, 2019
The estimation of interconnect consumption is important as it directly impacts the three main design constraints:Area consumption: The wires have to be placed somewhere on the chip. Especially structures such as busses require a large area.Delay consumption: The propagation delay is directly dependent on the length of the wires.Power consumption: The capacitance and resistance of the wires are dependent on the length of the wires, thus longer wires require more energy to transport a signal value.
Realization and Optimization of Combinational Circuits Using Simulated Annealing and Partitioning Approach
Published in IETE Journal of Research, 2023
Y.J. Pavitra, S. Jamuna, J. Manikandan
The Espresso logic synthesis tool is used to generate the solutions for benchmark circuits (realized using only AND, OR, and NOT gates) and the transistor equivalent is computed as per the details provided in Ref. [26]. CGP is the most widely used population-based genetic algorithm. The performance evaluation of the proposed work is computed with the transistor count obtained from Espresso and CGP with point mutation reported in Ref. [26]. The distance between the input to output decides the speed of the circuit as propagation delay increases with an increase in the number of levels. Level count optimization is considered the third objective function in the proposed work. As there is no report of level count for the benchmark circuits used in the proposed work, no comparison is provided for level count optimization. The best circuit obtained using the proposed work is compared with circuits reported in LGSynth’91 benchmark description, Espresso, and CGP and the results are reported in Table 3. It can be observed that the proposed work yielded optimal or near-optimal circuits (including overhead MUX) with 100% SR and 1-lakh generations over circuits realized using CGP with 10-lakh generations. It can also be noticed from Table 3 that the proposed work saved a maximum of 77.39% of gates and 98.61% of transistors over LGSynth’91 benchmark description, Espresso, and CGP, respectively.
A novel design of full adder cell for VLSI applications
Published in International Journal of Electronics, 2023
Onteru Anjaneyulu, C. V. Krishna Reddy
Speed of any digital circuit is one of the crucial parameters among the other and it is measured from propagation delay. The propagation delay is defined as change in the input voltage from 50% to change in output voltage to 50%. There are two types of delay times: (1) tphl input to output delay when the output switches from high to low level and (2) tplh input to output delay when the output switches from low to high level. The propagation delay is measured as average of tplh and tphl. It depends on various factors such as technology being used, type of topology adopted to implement it, rise and fall times, threshold voltage of the device, operating voltage and load capacitance. Another essential performance metric is the power dissipation. It depends on static power (due to leakage current), dynamic power (due to switching of output nodes) and short circuit power (a path establishes from supply to ground). The expression for average power dissipation of CMOS circuits is given by
CMOS electrochemical measurement circuit for biomolecular detection
Published in International Journal of Electronics, 2018
Wei-Chiun Liu, Shao-Te Wu, Bin-Da Liu, Chia-Ling Wei
The parameters of propagation delay and voltage offset are theoretically analysed using simulation for improving the output accuracy. The propagation delay is the amount of time between the input step excitation and the output signal response which achieves a new valid logic value. The propagation delay degrades overall chip performance. Thus, the practical design process must consider the comparator delay effects. In the simulation results of the process variations, Figure 4 shows the rising and the falling propagation delay of the continuous-time comparator, respectively. Table 2 shows the average propagation delay of each five-process corner variations and the maximum propagation delay time is 1780 ps. From the simulation results, the maximum propagation delay of the comparator has less interference and would not affect the system linearity in this work. Another important parameter influencing the accuracy of this comparator is the voltage offset which could be simulated as a deviation between the reference voltage of the transfer characteristic and the output signal. That is, when Vpo is placed nearby Vca, voltage offset could appear. Nevertheless, Vca, the external voltage, can be adjusted to avoid voltage offset before the measurement. Figure 5 shows the Monte Carlo simulation results with 400 trials when applying a 0.7-V input signal to Vca. The offset has an average value of 0.702 mV and a standard deviation of 0.007 mV in the simulation results. According to these Monte Carlo simulation results, the proposed comparator can reduce the effects of voltage offset and improve the output accuracy of this circuit.