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Novel Platforms and Applications Using Three-Dimensional and Heterogeneous Integration Technologies
Published in Katsuyuki Sakuma, Krzysztof Iniewski, 3D Integration in VLSI Circuits, 2018
Kuan-Neng Chen, Ting-Yang Yu, Yu-Chen Hu, Cheng-Hsien Lu
Heterogeneous integration is an important development direction for IoT cloud and smart life [9]. Furthermore, complementary metal–oxide–semiconductor–microelectromechanical systems (CMOS–MEMS) integration is critical in the future to sense the external environment. Advanced packaging technologies are developed to integrate different functions of the chips including sensor, logic, and memory. Among the packaging approaches, 3D/2.5D integration technologies have attracted attention because they are highly integrated, low weight, with high performance, and small form factor [10–11]. However, serious issues still exist in conventional sensor chip of 3D/2.5D integration. Due to the functionality of sensor chip, the surface morphology is quite different from circuit chip. The surface conditions of sensor chip usually have complex topography and brittle surface, even transparent material. Hence, the handling of sensor chip suffers throughput and alignment accuracy and becomes a bottleneck during assembly. Therefore, an alternative approach is needed to overcome the limitations.
The effects of pressure, temperature, and depth/diameter ratio on the microvia filling performance of Ag-coated Cu micro-nanoparticles for advanced electronic packaging
Published in International Journal of Smart and Nano Materials, 2022
Guannan Yang, Shaogen Luo, Bo Luo, Yan Zuo, Shiwo Ta, Tingyu Lin, Zhaohui Zhao, Yu Zhang, Chengqiang Cui
As electronic devices and integrated circuits continue to be driven toward high integration and miniaturization, advanced packaging technologies, such as 3D packaging and system-in-package, are attracting greater attention. Microvia filling is a fundamental technique for these advanced packaging technologies, as it provides channels for vertical electrical interconnection and signal communication between packaging layers, and thereby improves the communication rate and efficiency and reduces the volume and power consumption of electronic devices. With these advantages, microvia filling technology can be applied broadly in all levels of electronic packaging and manufacturing.
Cu metallisation on glass substrate with through glass via using wet plating process
Published in Transactions of the IMF, 2021
M. Takayama, K. Inoue, H. Honma, M. Watanabe
With the advent of the IoT (Internet of Things) era, enormous amounts of data are being successively accumulated through network connections. The range of application of large amount of data is being widened, and it will significantly change our lives and societies. Research and development of large-capacity and high-speed data communication technology as well as various sensors is being conducted as these comprise critical technology to realise new societies. Also, remarkable progress is being seen in new materials and nano-processing technology. In the field of electronics, finer patterning and higher integration are further promoted and high-performance circuit boards are required. Even greater insulating materials properties improvements and electronic device performances are being sought.1 The development of circuit boards using silicon for semiconductors is being pursued. In recent years, through silicon via (TSV)2 that has vias formed in silicon has been developed. Advances in semiconductor technology have made it possible to improve the degree of integration; for example, vertically stacking chips on a TSV substrate enabled the change from planar integration to three-dimensional integration of large scale integration (LSI). Accordingly, advanced packaging methods are being developed including 3D/2.5D packaging,3 Fan-Out4 that forms a redistribution layer on top of the wafer and expands (fans out) the contacts beyond the dimensions of the chip, and Embedded Multi die Interconnect Bridge (EMIB)5 that uses a very small silicon die with multiple routing layers, that serves as an in-package interconnect. For electronic devices, thin and small semiconductor devices that are integrated at high density and can operate at high speed will continuously be required.