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Advanced Flexible Hybrid Electronics (FHE)
Published in Katsuyuki Sakuma, Krzysztof Iniewski, Flexible, Wearable, and Stretchable Electronics, 2020
Takafumi Fukushima, Subramanian S. Iyer
A new concept of advanced FHE is based on cutting-edge semiconductor packaging technology of FOWLP (fan-out wafer-level packaging) in which thin dies, not ultrathin dies, are embedded in an epoxy mold compound (EMC). The resulting epoxy resin wafers with embedded thin dies can realize wafer-level processing. The communication between the neighboring dies is given by wafer-level metallization called redistribution layers (RDL), as shown in Figure 9.3. It has been reported that not only the device package height can be reduced but the performance of the holistic system is also drastically improved by FOWLP even with old-generation chips are used although it is the technology governed by the price [17, 18]. This outstanding packaging technology can push the performance scaling in spite of recent Moore's law limitations. We, at UCLA and Tohoku University, are inspired by FOWLP and have tried to apply this technology to create high-performance FHE with embedded rigid/thin/small dielets [19, 20]. The dielets are not bent and the bending of flexible links interconnecting the adjacent dielets gives high bendability to the advanced FHEs. The structural comparison between conventional FHE with an ultrathin/large die and advanced FHE with embedded rigid/thin/small dielets is shown in Figure 9.1b. Another advantage of our FHE is based on a modular “dielet” approach. In the dielet approach, instead of using one large application specific integrated circuits (ASIC) die, one can use multiple high-yielding smaller size dielets connected by lithographically defined metal interconnects at fine pitches (comparable to fat wire level) to allow for both higher mechanical flexibility and “on-chip”-like communication as shown schematically in Figure 9.1b.
Improved yield estimation with efficient decision power for multi-line processes
Published in Quality Engineering, 2021
Chia-Huang Wu, Ya-Chen Hsu, Wen-Lea Pearn
In flip-chip packaging, the Fan-Out Wafer Level Packaging (FOWLP) production process can reduce the cost without the problem of thickness and achieve high integration, at least theoretically. Utilizing FOWLP could lead to higher I/O, lower cost, thinner and smaller wafer packages, and better IC capacity and compatibility. When it comes to implementing FOWLP, underfill significantly affects the manufacturing yield and is a critical technology that is used to strengthen reliability. It is necessary to warm up the substrate to promote the fluidity of the glue first, before dispensing the underfill to the edge of the substrate. Capillary underfill is used to dispense the gap between the wafer and substrate and cure the glue through heating and hard baking (see Figure 1).