China
Africa
Explore chapters and articles related to this topic
White Light-Emitting Diode: Fundamentals, Current Status, and Future Trends
Published in Wengang (Wayne) Bi, Hao-chung (Henry) Kuo, Pei-Cheng Ku, Bo Shen, Handbook of GaN Semiconductor Materials and Devices, 2017
Bingfeng Fan, Yi Zhuo, Gang Wang
Here come two different approaches. One is chip-to-wafer wafer-level packaging. The LED units are diced off from the epi wafer first and then mounted on a carrier wafer as a package substrate. After subsequent wafer-level packaging process, the carrier wafer is diced into components. Since it still requires dicing the LED wafer, it is also regarded as semi WLP. In general, semi WLP processes require the patterned silicon submount wafer as a carrier. Through silicon vias (TSVs) may be built in for electric interconnection. Both wire bonding and flip-chip technology are feasible connection methods. Two examples corresponding to two different connection methods are shown in Figures 14.18 and 14.19 respectively [64,65].
MEMS-Based Wireless Communications
Published in Anwar Sohail, Raja M Yasin Anwar Akhtar, Raja Qazi Salahuddin, Ilyas Mohammad, Nanotechnology for Telecommunications, 2017
MEMS packaging costs account for 70%–90% of the device and 90% of the size. One way to reduce the cost of packaging and size for applications requiring large number of units is to use wafer-level packaging. Wafer-level packaging is increasing in importance because of low cost due to the batch character of the process and small size. In this packaging technique, structures are protected early in the process and testing can be done on the wafer. Wafer-level packaging also gives rise to smaller packages, better reliability, and better electrical properties due to the shorter paths used [[54].
Trends and challenges
Published in Andrea Chen, Randy Hsiao-Yu Lo, Semiconductor Packaging, 2016
Andrea Chen, Randy Hsiao-Yu Lo
Through-silicon via technology is considered to be a subset of wafer-level packaging. Through-silicon vias allow for stacked monolithic chips to communicate directly with one another, without the need for electrical signals to travel along wire bonds or flip-chip bumps, through substrate routing and onto another chip. As shown in Figure 9.5, such a configuration also reduces a package’s footprint.
Progress in wafer bonding technology towards MEMS, high-power electronics, optoelectronics, and optofluidics
Published in International Journal of Optomechatronics, 2020
Jikai Xu, Yu Du, Yanhong Tian, Chenxi Wang
Device packaging is one of the most important processes for MEMS fabrication. Because of the complex system, MEMS packaging has stricter requirements than the IC, such as ultralow stress, high vacuum, and precise alignment.[26–28] Correspondingly, the cost accounts for 50%-90% of the whole fabrication. To reduce costs and improve the working efficiency, wafer-level packaging has outstanding advantages in saving materials and labors compared with the component-level packaging.[29] Therefore, the development of wafer bonding technology has a profound influence on MEMS devices. Besides, Si is the basic platform for MEMS due to the low cost and mature fabrication technology. Most of the structural designs are based on the Si micro/nanofabrication process. In this section, we focus on the wafer bonding method for Si-based material in MEMS packaging, including eutectic bonding and direct bonding.
Improved yield estimation with efficient decision power for multi-line processes
Published in Quality Engineering, 2021
Chia-Huang Wu, Ya-Chen Hsu, Wen-Lea Pearn
In flip-chip packaging, the Fan-Out Wafer Level Packaging (FOWLP) production process can reduce the cost without the problem of thickness and achieve high integration, at least theoretically. Utilizing FOWLP could lead to higher I/O, lower cost, thinner and smaller wafer packages, and better IC capacity and compatibility. When it comes to implementing FOWLP, underfill significantly affects the manufacturing yield and is a critical technology that is used to strengthen reliability. It is necessary to warm up the substrate to promote the fluidity of the glue first, before dispensing the underfill to the edge of the substrate. Capillary underfill is used to dispense the gap between the wafer and substrate and cure the glue through heating and hard baking (see Figure 1).