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Machine Arithmetic
Published in Julio Sanchez, Maria P. Canton, Software Solutions for Engineers and Scientists, 2018
Julio Sanchez, Maria P. Canton
The 80386 processor introduced two new sign extension instructions designed to operate on 32-bit and 64-bit operands. CWDE (convert word to doubleword extended) converts a signed 16-bit number in AX into a signed 32-bit number in EAX. The CDQ (convert doubleword to quadword) assumes a two’s complement number in EAX and converts it into a signed 64-bit integer in EDX:EAX. The sign extension opcodes are useful in performing signed multiplication and division when one of the operands is in a different format than the destination. The following code fragment is a demonstration of the use of the CBW instruction.
Digital Logic, Arithmetic, and Conversions
Published in Julio Sanchez, Maria P. Canton, Microcontroller Programming, 2018
Julio Sanchez, Maria P. Canton
A simple mechanism for extending the capacity of two’s complement encoding is called sign extension. The process consists of copying the sign bit into the high-order bit positions of the extended encoding. For example, to extend a two’s complement 8-bit number into 16 bits, copy the sign bit of the original value (bit number 7) into all the bits of the extended byte. The process is shown in Figure 4-8 for both positive and negative operands.
Number Representation
Published in Wen-Long Chin, Principles of Verilog Digital Design, 2022
In the Verilog codes, the signed declaration is very handy for the signed number arithmetic because sign extension can be automatically performed by Verilog and synthesis tool.
VHDL implementation of 16x16 multiplier using pipelined 16x8 modified Radix-4 booth multiplier
Published in International Journal of Electronics, 2023
Radwa M. Tawfeek, Marwa A. Elmenyawi
Stage 2 contains two 18-bits adders: adder1 at the right and adder2 at the left. In all the adders of the design, a sign extension is performed whenever the number of bits of the two added numbers is not equal. In the case of YL, adder1 is used to add the remaining bits of PP1 (PP1(2) – PP1(16)) to their corresponding bits of PP2 (PP2(0) – PP2(16)). As illustrated in Figure 8(a), the bits PP3(1) and PP3(0) must be added to the sum result of PP1(5) to PP2(3) and PP1(4) to PP2(2) which are generated using adder1, these two bits are passed to the next stage. The remaining bits of PP3 (PP3(2)- PP3(16)) are added to their corresponding bits of PP4 using adder 2 as shown in Figure 9(a). The same scenario is repeated when processing YM for PP5, PP6, PP7, and PP8 as illustrated in Figure 9(b). The two least significant bits of adder1 in the case of YL are passed through the pipeline state registers to constitute the result bits (P3, P2) without any more processing. While in the case of YM, these two bits are passed to the final adder to be added to their corresponding PP bits.