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Arithmetic and Logic Unit Organisation
Published in Pranabananda Chakraborty, Computer Organisation and Architecture, 2020
Four basic arithmetic operations for fixed-point as well as for floating-point numbers are addition, subtraction, multiplication, and division. The arithmetic algorithms and the related logic circuits needed to implement these arithmetic operations are the main focus of this section and onwards. It has been shown that two n-bit signed numbers expressed in 2’s complement representation can be added/subtracted using n-bit binary addition/subtraction, treating the sign bit the same as the other bits. In other words, a logic circuit that is designed to add/subtract unsigned binary numbers can also be used equally well to add/subtract signed numbers in 2’s complement form. The time needed by an ALU to perform an arithmetic operation often influences the performance of the processor. Addition/subtraction in this regard takes relatively lesser time than multiplication and division which require more complex circuitry than either addition or subtraction operation. That is why, some modern techniques are used in today’s advanced computers that can perform all arithmetic operations at a comparatively higher speed.
Computer Architecture
Published in Bogdan M. Wilamowski, J. David Irwin, Fundamentals of Industrial Electronics, 2018
The mantissa is stored in a normalized sign-magnitude format. The sign bit is placed in the leftmost bit of the 32-bit code, allowing a number to be easily identified as positive or negative. The magnitude of the mantissa is of the form 1.F, where F is a 23-bit binary fraction stored in bits 22-0 for the single-precision format, and a 53-bit fraction stored in bits 52-0 for the double-precision format. Normalized forms are characterized by their most significant digits being nonzero, and are used to ensure a single unique representation for each floating-point number. For example, the following are a few of the many possible representations of the number 1408. 10.11×291.011×2100.1011×2110.01011×212
Data Converter Principles
Published in Tertulien Ndjountche, CMOS Analog Integrated Circuits, 2017
In the sign-magnitude representation, the bit in the MSB position is reserved for the number sign and the remaining bits indicate the number magnitude. The sign bit can be either 0 for positive numbers or 1 for negative numbers. The sign-magnitude representation has the drawback of having two different codes for zero and requiring a rather complex hardware for the realization of arithmetic operations.
Teaching redundant residue number system for electronics and computer students
Published in International Journal of Mathematical Education in Science and Technology, 2022
Let’s assume a two’s complement number Y and a k-digit BSD number A (in Figure 4) and. The bit representations of A and Y are as follows: To convert a k-bit two’s complement number Y to a k-digit BSD number A, the sign bit of the two’s complement number should be merely changed. The process of the conversion is performed as follows: That means the sign bit of a positive two’s complement number () is shown by , or . Also, the sign bit of a negative two’s complement number () is shown by . Therefore, binary to BSD forward conversion (Y to A) does not contain an important cost and is independent of the operand length. So,
Research and implementation of parallel artificial bee colony algorithm based on ternary optical computer
Published in Automatika, 2019
Shuang Li, Wenjing Li, Honghong Zhang, Zhehe Wang
In the search phase of the employed bees, each employed bee finds a new honey source by Equation (2) vij = xij + Øij(xij – xkj). By splitting Equation (2), it includes an addition, a subtraction and a multiplication. Addition uses a three-step adder, which requires three clock cycles to complete an addition. Since there is no sign bit in the MSD number, the subtraction is also implemented by the adder. It takes three clock cycles to complete one subtraction. One multiplication requires an M transform, which is one clock cycle, and requires layers of addition, that is 3log2SN clock cycles. Therefore, for a single calculation, a total of T = 7 + 3log2SN clock cycles are required.
Image compression and encryption scheme with hyper-chaotic system and mean error control
Published in Journal of Modern Optics, 2019
Ming-Jun Chen, Xiang-Tao He, Li-Hua Gong, Rong-Ling Chen
Step 4: A series of thresholds should be set to determine the importance of the DCT coefficients. The coefficients containing important information of the image are encoded as follows. As for the original coded bit plane , , is the sub-band coefficients as shown in Figure 3. Figure 3 shows the low-frequency coefficients of the sub-band. For an important coefficient, if , then the output is the most significant bit (MSB) of . For an unimportant coefficient, if , then the output is the sign bit of ; otherwise the output is .