China
Africa
Explore chapters and articles related to this topic
Arithmetic and Logic Unit Organisation
Published in Pranabananda Chakraborty, Computer Organisation and Architecture, 2020
In order to alleviate the limitations and drawbacks of the above-mentioned two methods, the most common scheme to represent negative numbers is 2’s (two’s) complement representation in which the most significant (leftmost) bit is also used here as sign bit. But it differs from the other two methods in the way in which the other bits of the integer are interpreted here. The 2’s complement of a positive number is obtained by taking the Boolean complement of each bit of the corresponding positive number (as is done in 1’s complement), and then adding 1 to the resulting bit pattern viewing it as an unsigned integer. Most important is that the number 0 is identified as positive, and therefore has a 0 sign bit and a magnitude of 0s in all remaining bits. For a n-bit positive number, the sign bit , bn − 1, is always zero, and the remaining bits in the number represent the magnitude of the number in the same manner as usual. Therefore, the range of positive integers that can be represented is from 0 to 2n− 1 − 1 (the largest integer is 2n− 1 − 1, with the sign bit zero, and all of the magnitude bits here are 1). Any large number beyond this range would then require more bits to represent. For a n-bit negative number, the sign bit, bn − 1, is 1, and the remaining n − 1 bits together can take on any one of the 2n− 1 values. Therefore, the range of the negative integers that can be represented with n bits is from −1 to −2n− 1.
Digital Circuit Design with Very-High-Speed Integrated Circuit Hardware Description Language
Published in A. Arockia Bazil Raj, FPGA-Based Embedded System Developer's Guide, 2018
std_logic_vector to Integer Using numeric_std: First, we need to think about the data that are represented by our std_logic_vector. Is it signed or unsigned data? Signed data mean that our std_logic_vector can be a positive or negative number. Unsigned data mean that our std_logic_vector is only a positive number. The example below uses the unsigned() typecast, but if our data can be negative, we need to use the signed() typecast. Once we cast our input std_logic_vector as unsigned or signed, then we can convert it to an integer as given below [15,16].
Basics of the central processing unit
Published in Joseph D. Dumas, Computer Architecture, 2016
It is possible to design half and full subtractor circuits that subtract one bit from another to generate a difference bit and a borrow out bit. A full subtractor is able to handle a borrow in, and a half subtractor is not. These blocks can then be cascaded together in the same fashion as adder blocks to form a ripple borrow subtractor. However, in practice, separate circuits are rarely built to implement subtraction. Instead, signed arithmetic (most frequently, two’s complement arithmetic) is used, with subtraction being replaced by the addition of the complement of the subtrahend to the minuend. Thus, one circuit can perform double duty as an adder and subtractor.
A novel coal-gangue recognition method in underground coal mine based on image processing
Published in International Journal of Coal Preparation and Utilization, 2023
Honglin Wu, Zhongbin Wang, Lei Si, Bin Liang, Dong Wei
The above processing result needs to be converted from the logarithmic domain to the real number domain (digital image). The logarithmic domain output is quantized to [0, 255]. In the process of algorithm implementation, the quality of the resulting image depends on the quality of the quantization method. In many versions of the modified MSRCR algorithm, the quantization method introduces many parameters, which cannot be automated. This study uses a fully automated quantitative method proposed in (Parthasarathy and Sankaran 2012), as shown in Fig. 3. This method selects the upper and lower clipping points of the gray histogram according to the frequency of pixel appearance. In the algorithm implementation, the gray data type is converted to a signed integer, and the frequency of occurrence of zero value is found from the histogram of the enhanced image and set to “max” The gray value corresponding to the frequency is used as the upper/lower clipping point. The pixels at both ends are discarded, and the y value determines the proportion of cropped pixels. After experiments, it is found that y = 0.05 is the optimal value for each type of image.
Influence of the multi-resolution technique on tomographic reconstruction in ultrasound tomography
Published in International Journal of Parallel, Emergent and Distributed Systems, 2021
Luong Thi Theu, Quang-Huy Tran, Vijender Kumar Solanki, Tatiana R. Shemeleva, Duc-Tan Tran
Let us consider work with variables in detail. Marking of Petri and Sleptsov nets represents directly nonnegative integer numbers, subnets for basic arithmetic operations specified in [14–17]. We suppose that in a similar way subnets for (signed) integer and real numbers are implemented using the technique for compressing a vector (matrix) as a nonnegative integer number [14,17]: an integer number is a vector of two components – sign and absolute value; a real number is a vector of four components – mantissa sign, mantissa absolute value, exponent sign, and exponent absolute value. The offered method uses matrices, which are packed into a nonnegative integer number [14,17]. To extract components of a matrix, we use a subnet eij (element in row i and column j) that is implemented using subnet MOD-DIV (modulo and division) [14,17]; for packing a matrix, subnet MUL-ADD (multiplication and addition) is applied [14,17].
Efficient FPGA-Based Real-Time Implementation of Model Predictive Control for Single-Phase Direct Matrix Converter
Published in Electric Power Components and Systems, 2021
By using (5) and (6), the resolution of each number involved in the control calculation can be adjusted. Adjusting fractional bits helps to reduce logic elements utilized by the FPGA. Full-scale implementation guarantees the best resolution and increases the precision of the declared variables. Full-scale implementation design steps of the MPC algorithm are tabulated in Table 2. The first step is to extract ADC values from the sensing board. In this work, the sensing board contains an ADC128S102 ADC chip from Texas Instruments, and it provides a 12-bit unsigned number for each measurement. The second step is to convert the ADC values to fixed-point signed format for the math calculations. The fixed-point signed format representation, which is shown in Table 2, for each measurement is < Sign Bit + Integer Bits> <Fractional Bits>. This conversion process depends on the scaling factor used by sensing circuits. Since voltage scaling factor and current scaling factor are different, integer word length for current measurement representation, which is 5 bits including a sign bit, is different from integer word length for voltage representation, which is 9 bits including sign bit. The current prediction and the cost function evaluation are done by using 32-bits signed format.