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A FinFET-Based Framework for VLSI Design at the 7 nm Node
Published in Krzysztof Iniewski, Santosh K. Kurinec, Sumeet Walia, Energy Efficient Computing & Electronics, 2019
Vinay Vashishtha, Lawrence T. Clark
A cell library requires Liberty timing characterization files (compiled into .db for Synopsys tools) as well as Layout Exchange Format (LEF) of the cell pins and blockages (FRAM for Synopsys). We have focused primarily on Cadence collateral, since we are most familiar with those tools. The technology LEF provides basic design rule and via construction information to the APR tool. This is a key enabling file for high quality; that is, low DRC count APR results. Additional files are the .cdl (spice) cell netlists. We provide Calibre PEX extracted, and LVS versions. The former allow full gate level circuit simulation without needing to re-extract the cells. Data sheets of the library cells are also provided. These are generated automatically by the Liberate cell characterization tool. Mentor Graphics Calibre is used for DRC, LVS and parasitic RC extraction. The parasitic extraction decks allow accurate circuit performance evaluation.
Design Databases
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC Implementation, Circuit Design, and Process Technology, 2018
Modern-day design databases contain constructs for dealing with timing-driven design and analysis. Parasitic elements represent the results of parasitic extraction, storing a network representing the full parasitic model, including resistor, capacitor, and inductor elements. It is possible to store a reduced form of the network, either as a pole-residue model or as a simpler Elmore model. It is necessary that each net be represented at a different level of abstraction, which reflects on the fact that the routing is fully complete for some nets but only partially complete for others. Timing models for Designs must be possible, and can serve both as the de facto model for leaf cells and as an abstraction for an intermediate-level Design. Constraints must be stored, both in the technology area (as definitions of operating conditions) and within the Design (as design-specific constraints). Timing arcs should be able to be stored, to allow for long-term lazy evaluation of timing information. Few modern databases contain much of this information. The Magma database contains most of it. OpenAccess contains everything but timing arcs and specific timing constraints, though a publically available extension includes these objects [44].
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Published in Richard C. Dorf, Circuits, Signals, and Speech and Image Processing, 2018
J. Gregory Rollins, Sina Balkir, Peter Bendix
Unfortunately, computer-aided simulation has its own problems: Real circuits are distributed systems, not the “lumped element models” which are assumed by simulators. Real circuits, therefore, have resistive, capacitive, and inductive parasitic elements present besides the intended components. In high-speed circuits these parasitic elements are often the dominant performance-limiting elements in the circuit, and must be painstakingly modeled. In addition, this modeling effort requires accompanying parasitic extractor software for the circuit under development. The results of parasitic extraction then need to be back-annotated to the original design for further verification and/or fine-tuning, rendering the overall design flow complicated.Suitable predefined numerical models have not yet been developed for certain types of devices or electrical phenomena. The software user may be required, therefore, to create his or her own models out of other models which are available in the simulator. (An example is the solid-state thyristor which may be created from a NPN and PNP bipolar transistor.)The numerical methods used may place constraints on the form of the model equations used.
A 56.6-63.1GHz LO generator with a low PN VCO and an ILFT
Published in International Journal of Electronics, 2022
Linhong Li, Di Zhu, Shuai Cheng, Niansong Mei, Zhaofeng Zhang
Parasitic extraction with starRC and EM-simulation are jointly performed to acquire reliable post-simulation results. The FTR of the proposed LOG is 56.6–63.1 GHz (10.9%). In order to manifest the discrete and continuous frequency tuning, the FTR curve of 20-GHz VCO is shown in Figure 13 , which is the function of tuning words (TW) and . Thanks to the improved PN of the S2 G feedback VCO, the proposed 60 GHz LOG performs admirably in the conversions from the circuit noises to PN. Figure 14 shows the results that at 1-MHz offset, the average PN is about −103 dBc/Hz, varying ±1 dB across the FTR while the PN at 10-MHz offset almost remains the same, which equals −125 dBc/Hz. Theoretically, the PN difference between fundamental VCOs and the final output of the ILFT at the same frequency offset has to conform to 20log3undefined.5, which is proved in Figure 14(b). The corner frequency is approximately plotted with the value of 331 kHz.
From Design to Tape-out in SCL 180 nm CMOS Integrated Circuit Fabrication Technology
Published in IETE Journal of Education, 2019
After completion of the layout design, its parasitic extraction is performed to find the parasitic resistances and capacitances corresponding to designed devices and interconnects. A netlist is thereby generated by appending such parasitics to the actual circuitry, which is utilised for post-layout simulation.