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Physical Design Automation
Published in M. Michael Vai, Vlsi Design, 2017
A non-exhaustive list of physical design tools includes layout editors, layout generators, design rule checkers (DRC), layout-versus-schematics verifiers (LVS), circuit extraction tools, and place-and-route tools. Layout editors and generators aid the time consuming and error prone layout production process. They are used to create library cells, and, in some situations, complete full-custom chip layouts. Design rule checkers and layout-versus-schematics verifiers ensure layout correctness. Circuit extraction tools generate simulation models from layouts. Place-and-route tools convert building block netlists (e.g., high-level synthesizer results) into physical layouts.
Digital IC Design for Transceiver SOC
Published in Kaixue Ma, Kiat Seng Yeo, Low-Power Wireless Communication Circuits and Systems, 2018
Wang Yisheng, Kaixue Ma, Kiat Seng Yeo
This is the final step to complete the design. Design Rule Check (DRC) used to confirm the design can be fabricated successfully. And Layout Versus Schematic (LVS) used to confirm the layout represents the corresponding schematic. For the digital design, netlist is used as a schematic in LVS.
A new CMOS compatible high performance first-order all-pass filter realisation
Published in Australian Journal of Electrical and Electronics Engineering, 2022
Bhartendu Chaturvedi, Jitendra Mohan, Shiv Narain Gupta
In this section, the layout of the proposed circuit is developed and various performance characteristics are investigated using the Cadence Analog Design Environment (ADE) with 0.18 µm gpdk technology. The body terminals of PMOS and NMOS transistors are connected to the most positive voltage (VDD) and most negative voltage (VSS), respectively. The developed layout of the proposed APF is shown in Figure 15. The given layout is successfully verified over the process of sequence such as design rule check (DRC) and layout versus schematic (LVS). The DRC validates the layout for any potential errors and yield rules. The LVS ensures that all of the nets on the layout match the schematic. Afterwards, the real parasitics are extracted from the developed layout. For the post-layout simulation verification, the R-C parasitic extracted view is used (Chen and Yang 2017). In the post-layout simulations, the circuit is supplied with ±1 V voltage sources while the bias current and passive capacitor are chosen as 100 μA and C = 90 pf, respectively. The layout of the proposed structure is found very compact and occupies only 43.70 μm × 50.02 μm area. Figure 16 demonstrates the pre and post layout simulation of gain and phase responses. The phase is found to vary from 0° to −180° and is −90° at the pole frequency. The pre-layout and post-layout simulation pole frequencies are determined to be 2.68 MHz and 2.57 MHz, respectively, with a 4.28% error. It is to be observed that there are minimal variations found between pre-layout and post-layout level simulation verifications. It also indicates that the performance of the layout structure is not much affected by device mismatches or any other statistical variations on device model (Biagetti et al. 2004; Conti et al. 1999, 2002; Crippa, Turchetti, and Conti 2002; Pelgrom, Duinmaijer, and Welbers 1989).