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Motivation Behind High Electron Mobility Transistors
Published in D. Nirmal, J. Ajayan, Handbook for III-V High Electron Mobility Transistor Technologies, 2019
A perspective view of a MESFET is given in Figure 1.5. It consists of a conductive channel with two ohmic contacts, one acting as the source and the other as the drain. The conductive channel is formed in a thin n-type layer supported by a high-resistivity semi-insulating (nonconducting) substrate. When a positive voltage is applied to the drain with respect to the source, electrons flow from the source to the drain. Hence, the source serves as the origin of the carriers, and the drain serves as the sink. The third electrode, the gate, forms a rectifying metal-semiconductor contact with the channel. The shaded area underneath the gate electrode is the depletion region of the metal-semiconductor contact. An increase or decrease of the gate voltage with respect to the source causes the depletion region to expand or shrink; this in turn changes the cross-sectional area available for current flow from source to drain. The MESFET thus can be considered a voltage-controlled resistor.
Digital Circuits
Published in Wai-Kai Chen, Analog and VLSI Circuits, 2018
John P. Uyemura, Robert C. Chang, Bing J. Sheu
A signal propagates through a transmission gate (TG) in a unique manner. In conventional logic gates, the input signal is applied to the gate terminal of an MOS transistor and the output signal is produced at the drain or the source terminal. In a TG, the input signal propagates between the source and the drain terminals through the transistor channel, while the gate voltage is held at a constant value. The TG is turned off if the voltage applied to the gate terminal is below the threshold voltage. The TG approach can be used in digital data processing to implement special switching functions with high performance as well as a small transistor count [1]. It also can be used in analog signal processing to act as a compact voltage-controlled resistor.
Semiconductor Devices
Published in Lev I. Berger, Semiconductor Materials, 2020
JFET is a voltage-controlled resistor. Its schematic structures are shown in Figures 8.23 and 8.24 (from References 8.12 and 8.15). The two p+-n junctions are separated by the n-type layer of the thickness 2a. When a reverse voltage drop Vg is applied to both gates (relative to the source), it forms two high-resistivity depletion regions of the thickness W in the n-layer. This decreases the cross section of the part of the channel through which electrons may pass from the source to the drain; the resistance of this narrowed part (active channel) is, therefore, increased. If a voltage VD is applied to the drain relative to the source, the current ID will flow toward the source. When ID is small, the geometry of the depletion area is the same as in the absence of a current. But, with the ID increase, the boundary between the channel and depletion area becomes more and more slanted (W is increasing along the direction of the conduction electron drift). This is a result of the increase of V(y) with y, and, therefore, the greater is y, the greater is the magnitude of the total (reverse) bias applied to the p*-n junctions. Increase of VD and, therefore, increase of ID result in decrease of W, and increase of W2. At a certain current ID = Ip and voltage VD = Vp (subscript p is for pinch-off), the depletion areas merge at the drain end of the channel and the current ID remains equal to Ip at any magnitude of VD > Vp. It is understandable that the greater is |vj, the smaller are magnitudes of the pinch-off current and voltage. A family of the I-V characteristics of a JFET is shown in Figure 8.25 (adapted from Reference 8.15).
A bridge technique for memristor state programming
Published in International Journal of Electronics, 2020
Mahdi Tarkhan, Mohammad Maymandi-Nejad, Sajad Haghzad Klidbary, Saeed Bagheri Shouraki
If can be generated from a control voltage signal, a voltage-controlled-resistor can be designed. The structure of such a circuit is demonstrated in Figure 4. Transistors NM5, NM6, PM5, and PM6 are utilised to pass the circuit input current to its other side. Based on the fact that this circuit is solely used in the programming phase, the current would be always positive, hence, it is not required to add complementary current mirrors to handle negative current. is a resistor which has a resistance proportional to of the target memristor (i.e. ). This resistor can be realised in chip based on the characteristics of the memristor used in the final product or for broader applications, an analog or digital potentiometer can also be attached externally using dedicated pins. Let us assume that the multiplier’s gain is equal to . Then, the input resistance of the circuit, i.e., can be obtained from the following equations:
Performance Enhancement of Capacitance-Type Level Measurement System using CCII-Based Interface
Published in IETE Technical Review, 2020
Different types of interfaces have been discussed till date for the measurement of any type of capacitance sensor [13–18]. Generally, the design of capacitance sensor interfaces can be based on bridge topology, oscillator topology or current-mode topology. Bera et al. in [3] and [12] have designed Modified De’Sauty bridge circuit powered by Wien bridge oscillator using op-amp which is used to measure the capacitance of the level sensor. Mantenuto et al. in [13] have proposed four interfaces for measuring the capacitance. In three of four interfaces, they have proposed Voltage Controlled Resistor (VCR) to modified-De’Sauty bridge topology. Automatic tuning of one and/or two VCRs is done with a suitable feedback loop to handle bridge differential output voltage and phase. Further improvement in this topology provides a solution to estimate the parasitic resistive component which alters the sensor’s ideal behaviour. In the fourth interface, an alternative approach for implementing phase difference has been taken into account with the help of XOR gate and zero-crossing detectors. In [14], Marcellis et al. proposed a current-mode square wave generator, based on the second-generation current conveyor (CCII) for measurement of resistive/capacitive sensors. For a wide range of capacitive/resistive sensors, this interface converts impedance to time-period. Here, DC biasing voltage only to the ICs of the interface is required instead of providing AC excitation to the whole circuit. Sagar et al. presented a capacitance-type level measurement system for cryogenic and room temperature applications in [15]. LC oscillator-based signal conditioning unit is coupled with capacitance level sensor to measure the level of Liquid Nitrogen. The frequency of oscillator changes with the change in capacitance of level sensor caused due to the change in liquid level.
Electrical oscillation generation with current-induced resistivity switching in VO2 micro-channel devices
Published in Science and Technology of Advanced Materials, 2018
Milinda Pattanayak, Md Nadim F Hoque, Zhaoyang Fan, Ayrton A. Bernussi
The S-type I–V curves exhibited by the two-terminal VO2 devices (see Figure 3) are characterized by the two threshold voltages Vth1 and Vth2 corresponding to the forward and reverse IMT, respectively. When the device is supplied by a constant current, higher than the aforementioned threshold current, the corresponding voltage across the device cannot increase instantaneously. Instead, it rises exponentially similar to a capacitor charging (see Figures 4–6 and 7(b)). After Vth1 is reached, the VO2 channel transforms into the metallic state creating a current flow path parallel to the internal capacitor (see inset of Figure 7(a)). A rapid relaxation of the capacitor charge occurs through the highly conductive channel. As a result, the voltage across the channel becomes lower than Vth2, which is not sufficient to hold it in the metallic state since the current magnitude is limited. As the voltage across the channel drops below Vth2, the reverse IMT occurs and the channel transforms back into the insulating state. This process is repeated to keep the current constant and then the oscillation is observed. The DC power source supplies a constant current while the voltage changes to drive the same current through the changing channel resistance. Therefore, the oscillation is a consequence of charging and discharging of the internal capacitor due to changes in the VO2 channel resistance. Such oscillation can be modelled using an equivalent circuit approach. We implemented an equivalent circuit model using the SPICE simulation software to model the observed oscillation waveforms in our experiments. Figure 8(a) shows the circuit equivalent model used to generate the oscillatory response under similar biasing conditions [22]. The VO2 micro-channel device is represented by the voltage-controlled resistor Rchannel, which is a function of the voltage drop (Vchannel) across the channel. The state of the device (insulator or metallic) is controlled by an ideal op-amp and it is stored inside the output capacitor (Co). The voltage (V+) at the non-inverting terminal is the sum of two dependent voltage sources represented by the following relation [26]: