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A wide-tuning frequency range DLL-based clock generator
Published in Artde D.K.T. Lam, Stephen D. Prior, Siu-Tsen Shen, Sheng-Joue Young, Liang-Wen Ji, Smart Science, Design & Technology, 2019
Almost all electronic systems have a clock generator [1], and the clock generator determines the speed of the whole system, a good clock generator can greatly improve the performance and adaptability of the system. There are two ways to implement the general clock generator. One is to use the crystal oscillator. The other is to use the circuit technique and the crystal oscillator to realize the high speed and wide-tuning range of the clock generator. The crystal oscillator only generates a single frequency, which is only suitable for low-speed and simple systems. Generally, circuit techniques are used to improve output frequency of the crystal oscillator in order to make the system more high-speed and flexible. The circuit implementations are mostly divided into two methods .One is Phase Locked Loop (PLL)[2-3] the other is realized by using Delay-Locked Loop (DLL)[4-6] .The implementation of PLL has the advantages of high speed, easy to change the output frequency, and has many applications. Compared with the PLL-based clock generator, the DLL has many advantages, such as smaller area, faster locking time, unconditional loop stability and better performance of clock jitter. Therefore, in recent years, DLL is often used to replace PLL.
Clock Network Design: Basics
Published in Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar, Handbook of Algorithms for Physical Design Automation, 2008
Jitter is another measure of the variation in the arrival time of a clock transition. Specifically, it refers to the temporal variation of the clock period at a given point on the chip. Like skew, it is an important metric to the quality of the clock signal because it also forces designers to be conservative and use a longer clock period. The structure of the clock network has insignificant effect on jitter. Jitter is caused by delay variation in clock buffer due to power supply noise and temperature fluctuation, influence of substrate/power supply noise to the clock generator, capacitive coupling between clock and adjacent signal wires, and data-dependent nature of load capacitance of latch/register [1]. It is more effectively minimized by the design of other components like power supply network and clock generator. Therefore, it is typically not considered during clock network design.
FlexRay Protocol
Published in Nicolas Navet, Françoise Simonot-Lion, Automotive Embedded Systems Handbook, 2017
Bernhard Schätz, Christian Kühnel, Michael Gonschorek
In a TDMA network such as FlexRay, all nodes of a cluster need a common global clock so that every node will only send in its time slot(s). At the startup of the system all local clocks of the nodes have to be synchronized to provide this global time. Each node has a local clock generator, usually based on the resonance frequency of a quartz crystal. As two crystals rarely have exactly the same resonance frequency, the local clock start drifting apart during operation. A typical quartz crystal has a precision in the magnitude of 50 ppm. The frequency of a crystal cannot be determined statically, since it is also influenced by external factors such as temperature and vibration [WG92]. So the local clocks have to be synchronized regularly during operation of the system.
Reconfigurable radio receiver with fractional sample rate converter and multi-rate ADC based on LO-derived sampling clock
Published in International Journal of Electronics, 2018
Sungkyung Park, Chester Sungchung Park
Since the continuous-time delta-sigma ADC is typically sensitive to its sampling clock noise, phase noise and timing jitter should be examined for our sampling clock generator. The close-in phase noise at the output of the frequency divider in the sampling clock generator is smaller than that at the input of the frequency divider while the timing jitter value stays, assuming the inherent noise of the sampling clock generator itself is negligible. Through frequency division, only the number of rising (or falling) edges decreases and the noise characteristic of each edge is unchanged. The close-in phase noise drops after frequency division since the period Tout is increased and Δϕout = ΔTout/Tout×2π. In practice, the uncertainty in the propagation delay of each part comprising the sampling clock generator causes jitter. In order to reduce the jitter contributed by the inherent noise in the frequency divider, low-noise design techniques (Kroupa, 2001) including resynchronisation using a clean clock may be adopted. The resulting phase noise at the output of our sampling clock generator is simulated and plotted in Figure 7, assuming the input LO signal is an ideal clock. The resulting phase noise corresponds to an rms jitter well below 100fs, which validates the assumption made in Ch. 1 that the jitter contributed by the sampling clock circuitry itself is negligible compared with the jitter from the LO.
A 25-GS/s 6-bit time-interleaved SAR ADC with design-for-test memory in 40-nm low-leakage CMOS
Published in International Journal of Electronics, 2019
Long Zhao, Bao Li, Yuhua Cheng
The ADC core consists of three main blocks, the interleaving sampling structure, the clock generator and the single-channel SAR ADC. The interleaving sampling structure is critical for the sampling speed, bandwidth and distortion. The quality of the sampling clocks such as random jitter and timing skews is determined by the clock generator. The single-channel ADC limits the resolution and has a great impact on the power consumption.