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Recent Advances in Positron Emission Tomography Technology
Published in Krzysztof Iniewski, Biological and Medical Sensor Technologies, 2017
Farhad Taghibakhsh, Craig S. Levin
This is a novel technology recently developed by Philips which integrates an SiPM with processing circuits at microcell level to produce an all-in-one digital sensor that considerably reduces the need for external processing circuitry. Each device contains an integrated counter and an integrated time to digital converter (TDC) to provide energy and arrival time information (Figure 15.6), respectively [18]. In these devices, each detected photon is directly converted into a digital signal in each of the Geigermode cells of the sensor. Integration of the TDC with the digital sensor provides excellent timing resolution of 153 ps FWHM, while the reported energy resolution is 10.4% FWHM when the sensor is coupled to a 4 × 4 × 22 mm3 LYSO crystal [19]. The sub-200 ps timing resolution for digital SiPM suggests that the detector is promising for time of flight PET applications.
All-Digital Noise-Shaping Time-to-Digital Converters for Mixed-Mode Signal Processing
Published in Christopher Siu, Krzysztof Iniewski, IoT and Low-Power Wireless, 2018
The advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has resulted in a sharp increase in the time resolution of digital circuits and a rapid deterioration of the performance of mixed analog-digital circuits arising from a shrinking voltage headroom, worsening device match, deteriorating linearity, and disturbances coupled from neighboring digital blocks. Time-mode signal processing where information is represented by the difference between the occurrence of two digital signals offer a viable and technology-friendly means to combat technology scaling induced challenges encountered in the design of mixed analog-digital systems. Time-to-digital converters (TDCs) that map a time variable to a digital code are the most important building blocks for time-mode signal processing [1]. Although the deployment of TDCs in time-of-flight measurement dates back to 1970s [2, 3], the applications of TDCs in mixed-mode signal processing such as analog-to-digital converters (ADCs) [4–6] and phase-locked loops (PLLs) [7, 8] emerged recently. TDCs can be loosely classified into sampling TDCs such as delay-line TDCs [9–11] and noise-shaping TDCs such as gated ring oscillator (GRO) TDCs [5]. Sampling TDCs suffer from a low time resolution due to the absence of a noise-suppressing mechanism capable of lowering quantization noise to below gate delay. Although a high resolution can be obtained using vernier TDCs [9, 10, 12, 13] or pulse-shrinking TDCs [14, 15], both are at the expense of excessive silicon area and power consumption. Noise-shaping TDCs achieve a high time resolution by displacing a portion of in-band quantization noise to frequencies outside signal band. TDCs with a high time resolution are pivotal to applications such as all-digital PLLs (ADPLLs), where TDCs function as a phase detector. As the quantization noise of TDC phase detectors directly affects the overall phase noise of ADPLLs, minimizing the quantization noise of TDCs within the loop bandwidth of ADPLLs is critical.
A 5.4 ps resolution TDC design with anti-PVT-variation mechanism using 90-nm CMOS process
Published in International Journal of Electronics, 2023
Chua-Chin Wang, Oliver Lexter July A. Jose, Akhil Avilala
Time-to-digital converters (TDC) are very popular ADC circuits in an application that requires high time resolution measurement (Machado et al., 2019). The primary concept of TDC is to determine the time interval between two signals, namely the”start” and”stop” signals, and provide a binary code equivalent to the time difference (Palani et al., 2020). One parameter that will measure the performance of an ADC is its resolution. So is TDC. An ADC’s resolution is the highest conversion ratio from analogue to digital signal without oversampling. The time resolution defines the time measurement performance. It presents the sampling step as well as the smallest time interval that may be observed. The resolution of the ADC must be kept high to get optimal performance (Feng et al., 2010). Other parameters can characterise and affect in the TDC performance evaluation such as its dynamic range and latency. Different designs and architecture of TDCs have been presented with low power consumption and very simple circuit structures.
Adaptive timing correction technique for pulse-amplitude and pulse-position modulation interface
Published in International Journal of Electronics, 2019
Waleed Madany, Mostafa Rashdan, El-Sayed Hasaneen
Different time-based serial link architectures are proposed as an alternative to SerDes architectures. In (Rashdan, Abdel, Haslett, & Maundy, 2009), the authors have proposed a PPM-TDC serial link. The position of the rising edge of the input clock signal is modulated at the transmitter side. At the receiver side, the time difference between the received data signal and the received clock signal is then converted to a digital code using a time-to-digital converter (TDC) circuit. In these links, the operating frequency of the input clock signal is not proportional to the number of the transmitted data bits, which permits increasing the data rate without complicating the link design as in SerDes links (Rashdan et al., 2009).