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Input–Output Organisation
Published in Pranabananda Chakraborty, Computer Organisation and Architecture, 2020
A bus that connects major computer components such as CPU, memory, and I/O is called a system bus. It usually consists of, typically, 50–100 parallel copper lines providing different functions etched onto the motherboard, with connections spaced at regular intervals for plugging in memory, I/O, and other add-on cards. Although there are many different bus designs, on any bus, these lines can be classified into three basic functional groups: data lines, address lines, and control lines. In addition, there may be power distribution lines that supply power to the attached modules. Each of these groups, however, carries various types of signals indicating respective operations to be performed.
Design and Functional Modules of Digital Protective Relays
Published in Vladimir Gurevich, Digital Protective Relays, 2017
The system bus provides communication between various elements of the microprocessor. The bus is a group of conductors used as communication lines for transmitting digital data. There are three main types of buses in the microprocessor: a data bus, address bus, and control bus. The data bus provides data transfer between processor assemblies. The address bus is used to transfer the memory cell address to obtain data from the permanent storage or random access memory. The control bus transmits control signals from the microprocessor to other system elements.
Computer Systems
Published in Sharon Yull, BTEC National for IT Practitioners: Core Units, 2009
To allow communication between different parts of the computer system, a ‘bus’ system is required. A bus is a group of parallel wires along which data can flow. The system bus is made up of a number of such communication channels that connect the processor and other components such as memory, input and output devices together. A computer will normally have several buses that are used for specific purposes.
Risk-based optimal operation of hybrid power system using multiobjective optimization
Published in International Journal of Green Energy, 2020
The state of charge (SOC) of battery for case 1 is depicted in Figure 2. Any voltage within the minimum and maximum limits is acceptable from the system operations point of view. However, by optimizing the total operating cost objective, there might be a small reduction in voltages, but they are all within the limits. The obtained system bus voltages in this case are depicted in Figure 3. The system power losses incurred in this case are 9.481 MW. The total power generation cost obtained in this case is 901.32 $/h, and the mean adjustment cost (MAC) to handle the uncertainties is 64.05 $/h. Therefore, the total operating cost obtained in this case is the sum of total generation cost and MAC, which is 965.37 $/h. The CVaR obtained in this case is 1067.58 $/h2. The simulation time required for solving Case 1 using EGA is 31.660 s.
Decoupled State-Feedback Based Control Scheme for the Distributed Generation System
Published in Electric Power Components and Systems, 2018
where , R is a series resistance between the system bus and the DG bus. Rp and C are the parallel resistance and the equivalent capacitor used in the DC side of the inverter (not shown in Figure 1), and L is an inductance between the system bus and the DG bus. V and E are the voltage of the power system and the voltage of the DGU as shown in Figure 1, respectively. The phase “a” is aligned with the d-axis; consequently, Vq−sys is set to zero. The power references (active and reactive) are related to the current references (direct and quadrature) through the matrix equation given as [3]:
Designation of Optimal Location of Phasor Measurement Units by Comparing Different Methods for Türkiye 400 kV Power Systems
Published in Electric Power Components and Systems, 2022
Beytullah Bozalı, Ali Öztürk, Salih Tosun
After carefully examining the literature for the IEEE 14 -bus system, it was seen that similar results are similar. For example, in the articles about DFS [32, 33, 44, 47, 49, 57], GTh [32, 33, 47, 57], and SA Method [32, 33, 44, 49, 57, 58], information was provided about several PMUs and location similar to ones provided in Table 1. The results show that the methods used are consistent with the findings in the literature. In addition, the MSA Method, which is an enhanced version of the SA Method, was developed and applied to the power system as a new method. For the IEEE 14-bus testing system, there are different solutions for the locations and the number of PMUs that make the system fully observable. Different solutions making the entire system observable with the minimum number of PMUs can be achieved. The MSA Method generates solutions in such a way. According to the literature review, the best PMU placement solution results for the IEEE 14-bus test system were found as 4 PMU devices. Different methods such as GFS, GTh, and SA were used in the solutions. In this study, it was determined that even the whole system can be observed with the 3 PMU device. By using MSA, IEEE 14 Bus System Optimal PMU Placement results were shown in Table 1. A bus without any generators or load connected is called a ZIB. ZIB has no load or generator. For example, in IEEE 14 bus system, bus 7 is a ZIB. The existence of ZIB can also help reduce the number of PMUs needed. Accordingly, there is no need to place a PMU on bus 7 in the IEEE 14 Bus Test System. IEEE 14 Bus Power Test System can be fully observed with 3 PMU devices. Using the MSA Method, PMUs are located at buses 2, 6, and 9 in IEEE 14 bus system.