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VLSI Testing
Published in Santanu Chattopadhyay, Thermal-Aware Testing of Digital VLSI Circuits and Systems, 2018
A stuck-at fault affects the signal lines in a circuit such that a line has its logic value permanently as 1 (stuck-at-one fault) or 0 (stuck-at-zero fault), irrespective of the input driving the line. For example, the output of a 2-input AND-gate may be stuck-at 1. Even if one of the inputs of the AND-gate is set to zero, the output remains at 1 only. A stuck-at fault transforms the correct value on the faulty signal line to appear to be stuck at a constant logic value, either 0 or 1. A single stuck-at fault model assumes that only one signal line in the circuit is faulty. On the other hand, a more generic multiple stuck-at fault model assumes multiple lines become faulty simultaneously. If there are n signal lines in the circuit, in a single stuck-at fault model, the probable number of faults is 2n. For a multiple stuck-at fault model, the total number of faults becomes 3n−1 (each line can be in one of the three states—fault free, stuck-at 1, or stuck-at 0). As a result, multiple stuck-at fault is a costly proposition as far as test generation is concerned. Also, it has been observed that test patterns generated assuming a single stuck-at fault model are often good enough to identify circuits with multiple stuck-at faults also (to be faulty).
Design Automation Technology Roadmap
Published in Wai-Kai Chen, Computer Aided Design and Design Automation, 2018
To bound the test generation problem, a model was developed to represent possible defects at the abstract gate level. This model characterizes the effects of defects as stuck-at values. This model is fundamental to most of the development in test generation and is still in use today. It characterizes defects as causing either a stuck-at-one or a stuck-at-zero condition at pins on a logic gate. It assumes hard faults (i.e., if present, a fault remains throughout the test) and that only one fault occurs at a time. Thus, this model became known as the single stuck-at fault model. Stuck-at fault testing assumes that the symptom of any manufacturing defect can be characterized by the presence of a stuck-at fault some place within the circuit and that it can be observed at some point on the unit under test. By testing for the presence of all possible stuck-at faults that can occur, all possible manufacturing hard-defects in the logic devices can thus be tested.
Fundamentals of Small-Delay Defect Testing
Published in K. Goel Sandeep, Chakrabarty Krishnendu, Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits, 2017
M. Reddy Sudhakar, Maxwell Peter
The line stuck-at fault model has been the most widely used fault model for more than fifty years. This fault model associates with every circuit line two faults called stuck-at-0 and stuck-at-1. When a line, say l, is stuck-at-0 (1), then independent of the circuit inputs line l will be at logic value 0 (1). Thus, a stuck-at fault may change the functionality of the circuit. Notice that a line stuck-at fault accurately models a defect that causes a zero- (low-) resistance short between a line and power supply rails. Typically, a single line in the CUT is assumed to be stuck-at-0 or stuck-at-1. In this case, the fault model is often referred to as the single (line) stuck-at fault model. If the circuit has N lines, then the number of faults in the single stuck-at fault model will have 2*N faults.
Characterization of Test Sets for Multiple Faults in Combinational Network
Published in IETE Journal of Education, 2021
The problems of determining whether a digital circuit operates correctly or not are both of practical importance and theoretical concern. Combinational logic circuits form the vital parts of a digital system. Hence fault detection of combinational logic circuits has received much attention. One way of knowing whether a combinational logic circuit with n primary inputs operates correctly is by applying to the circuit all possible 2n primary input patterns and comparing the resultant primary outputs with those given by the corresponding truth table of the fault-free version of the same circuit. If there exists a conflict for at least one of the 2n primary input patterns, then a fault exists in the network. Otherwise, the network will be fault free. Such an exhaustive testing of a combinational network will be very much time-consuming in case of a complex circuit. To address this problem, algorithmic test pattern generation [1–8], has been developed. Most of the well-known fault detection techniques are based on stuck-at fault model according to which the fault on a line of a combinational circuit can be either stuck-at-zero () or stuck-at-one (). Techniques based on single stuck-at fault model as well as multiple stuck-at fault model are available in the literature. It is recognized that multiple fault testing is not usually worth the effort since single fault testing catches the faults all at a time. However, there exist some works on multiple fault testing [4, 5, 8]. Among them, there are some heuristic techniques [4, 5] based on the notion of Boolean differences. Boolean difference [3, 5–7] is a straight forward and analytical tool for fault detection. The first-order Boolean difference (denoted by ) of the Boolean function with respect to , is defined as This definition of first-order Boolean difference can then be extended to obtain various higher order Boolean differences, the p-th order Boolean difference of the Boolean function being defined as