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Automatic Test Pattern Generation
Published in Louis Scheffer, Luciano Lavagno, Grant Martin, EDA for IC System Design, Verification, and Testing, 2018
Kwang-Ting (Tim) Cheng, Li-C. Wang
Historically, ATPG has focused on a set of faults derived from a gate-level fault model. For a given target fault ATPG consists of two phases: fault activation and fault propagation. Fault activation establishes a signal value at the fault site opposite that produced by the fault. Fault propagation propagates the fault effect forward by sensitizing a path from the fault site to a primary output. The objective of ATPG is to find an input (or test) sequence that, when applied to the circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by a particular fault. Effectiveness of ATPG is measured by the fault coverage achieved for the fault model and the number of generated vectors, which should be directly proportional to test application time.
Test Technology for Sequential Circuits
Published in Vojin G. Oklobdzija, Digital Design and Fabrication, 2017
H.T. Vierhaus, Zoran Stamenković
An ATPG tool uses deterministic test pattern generation when it creates a test pattern intended to detect a given fault. The procedure is to pick a fault from the fault list, create a pattern to detect the fault, simulate the pattern, and check to make sure the pattern detects the fault. More specifically, the tool assigns a set of values to control points that force the fault site to the state opposite the fault-free state, so there is a detectable difference between the fault value and the fault-free value. The tool must then find a way to propagate this difference to a point where it can observe the fault effect. To satisfy the conditions necessary to create a test pattern, the test generation process makes intelligent decisions on how best to place a desired value on a gate. If a conflict prevents the placing of those values on the gate, the tool refines those decisions as it attempts to find a successful test pattern. If the tool exhausts all possible choices without finding a successful test pattern, it must perform further analysis before classifying the fault. Faults requiring this analysis include redundant, ATPG-untestable, and possible-detected-untestable categories. Identifying these fault types is an important by-product of deterministic test generation and is critical in achieving high test coverage. For example, if a fault is proven redundant, the tool maysafely mark it as untestable. Otherwise, it is classified as a potentially detectable fault and counts as an untested fault when calculating test coverage.
Automatic Test Pattern Generation
Published in Luciano Lavagno, Igor L. Markov, Grant Martin, Louis K. Scheffer, Electronic Design Automation for IC System Design, Verification, and Testing, 2017
Kwang-Ting (Tim) Cheng, Li-C. Wang, Huawei Li, James Chien-Mo Li
Historically, ATPG has focused on a set of faults derived from a gate-level fault model. For a given target fault, ATPG consists of two phases: fault activation and fault propagation. Fault activation establishes a signal value at the fault site opposite to that produced by the fault. Fault propagation propagates the fault effect forward by sensitizing a path from the fault site to a primary output (PO). The objective of ATPG is to find an input (or test) sequence that, when applied to the circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by a particular fault. Effectiveness of ATPG is measured by the fault coverage achieved for the fault model and the number of generated vectors, which should be directly proportional to test application time.
Power-Aware Testing for Maximum Fault Coverage in Analog and Digital Circuits Simultaneously
Published in IETE Technical Review, 2022
Vivek Kumar Singh, Trupa Sarkar, Sambhu Nath Pradhan
A recent trend in the semiconductor technology towards integrating analog and digital cores in the same chip has increased the complexity in SOC. Most of the SOCs used now-a-days are mixed-signal circuits, which are embedded with analog and digital circuits [1,2]. Compared to that of digital testing the test cost of mixed-signal SOC is significantly higher. Faults in analog circuits are catastrophic faults (hard faults) and parametric faults (soft faults), whereas digital testing uses simple fault models such as stuck-at faults. In mixed-signal testing, the real problem is the observability and controllability of all the blocks because there cannot be a direct access to analog outputs or digital inputs. So, the testing of these types of mixed circuits is much tougher than only digital or only analog ICs. Generally, for digital fault detection, various automatic test pattern generators (ATPG) have been developed over the years to get test patterns. But in mixed SOCs, test patterns cannot be delivered directly to the digital circuit as there may be some analog or data converter present before that. So, the solution to this problem is to create a test signal such as a sinusoidal signal for the analog block. This signal is applied at the input of the analog block. Then using the output of the analog circuit, the data converter (ADC) produces a digital test pattern to check for the digital faults in the digital circuit. Hence using only one ATPG, both blocks can be tested, which results in a cost-effective and less time-consuming testing procedure. As we know that a mixed-signal circuit contains analog and digital blocks interfaced by a converter circuit (ADC/DAC), the testing of the mixed-signal circuit is also classified into analog and digital signal testing. Digital testing is quite simpler and popular than analog testing due to the structuralism nature and adaptive nature to the computer tools. The disparity between these two testing approaches is acute in the sense of test pattern generation. In digital testing, the BIST technique [3] is implemented from the primitive stage of testing. In addition, fault simulation is often used to assess the effectiveness of a set of test vectors in detecting faults that might occur during manufacturing.