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Code Coverage Metrics
Published in Chris Hobbs, Embedded Software Development for Safety-Critical Systems, 2019
When we perform a test, we actually want to achieve a high fault coverage — that is, we want to execute tests that expose faults. However, the number of faults in the code is unknown, and so measuring the level of fault coverage is impossible. Instead, the level of branch or MC/DC coverage is used as a proxy for fault coverage, and a reasonable question is, “Does x% of branch or y% of MC/DC coverage correlate with a particular level of fault coverage?”
Application-Specific Integrated Circuits
Published in David R. Martinez, Robert A. Bond, Vai M. Michael, High Performance Embedded Computing Handbook, 2018
M. Michael Vai, William S. Song, Brian M. Tyrrell
As noted above, except for very small circuits, it is impractical to pursue an exhaustive test. Instead, a test should consist of a set of test patterns that can be applied in a reasonable amount of time. This test should provide the user with the confidence that the chip under test is very likely to be fault free if it passes the test. An important issue in the development of a test procedure is thus to evaluate the effectiveness of a test. The quality of a test can be judged by an index called fault coverage. Fault coverage is defined as the ratio between the number of faults a test detects and the total number of possible faults. This is usually determined by means of a simulated test experiment. This experiment, which is called a fault simulation, uses a software model of the chip to determine its response to the test when faults are present. A fault is detected by a test pattern if the circuit response is different from the expected fault-free response.
VLSI Testing
Published in Santanu Chattopadhyay, Thermal-Aware Testing of Digital VLSI Circuits and Systems, 2018
As the types of defects in a VLSI chip can be numerous, it is necessary to abstract them in terms of some faults. Such a fault model should have the following properties: Accurately reflect the behavior of the circuit in the presence of the defect.Be computationally efficient to generate test patterns for the model faults and to perform fault simulation for evaluating the fault coverage.
An efficient phased-mission reliability model considering dynamic k-out-of-n subsystem redundancy
Published in IISE Transactions, 2018
Suprasad V. Amari, Chaonan Wang, Liudong Xing, Rahamat Mohammad
In this article we make contributions to the topic area by proposing an exact and efficient method for the reliability analysis of a special class of PMSs with multiple k-out-of-n subsystems and identical components within each subsystem. As the majority of PMSs used in safety-critical or mission-critical applications are non-repairable during the mission, we mainly focus on non-repairable PMSs. Also, in this article we assume that the sequence of phases is predefined. All the failures can be perfectly located and covered, that is, imperfect fault coverage is not considered in this work. Refer to Xing (1997), Xing et al. (2012) and Peng et al. (2014) for the reliability analysis of PMSs with imperfect fault coverage. Efficiency of the proposed method is demonstrated through analyses of medium-scale to large-scale systems.
Memory-Efficient LFSR Encoding and Weightage Driven Bit Transition for Improved Fault Coverage
Published in IETE Journal of Research, 2023
Benchmark circuits are set of digital combinational and sequential circuit that helps in comparing ATPG (Automatic Test Pattern Generator) tools. In this section, experiments are conducted on large sets of ISCAS ‘85 and some combinational parts of ISCAS ‘89 benchmarks circuits to validate the effectiveness of the proposed TPG. Here, test patterns are targeted to complete fault coverage over random stuck-at faults. For each CUT, LFSR is practiced to generate only randomized test patterns for all stuck-at faults targeting at 100% fault coverage.
Utilizing Sneak Paths for Memristor Test Time Improvement
Published in IETE Journal of Research, 2023
Fault coverage is a ratio of the total number of faults detected to the total faults possible in the memristor circuit for a given test vector set. The number of test vectors (IO switch-vectors) in a test vector set can be reduced by utilizing long sneak paths. The sneak paths longer than three memristors are referred to as long sneak paths. The following example for fault coverage uses five memristor long sneak paths. Using these long length sneak paths, any faulty memristor along the long sneak path is detected.