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Logic Circuits and Applications
Published in Muhammad H. Rashid, Ahmad Hemami, Electricity and Electronics for Renewable Energy Technology, 2017
The output is represented by Q=A+B¯ XOR Gate
Novel PVT Resilient Low-Power Dynamic XOR/XNOR Design Using Variable Threshold MOS for IoT Applications
Published in IETE Journal of Research, 2023
Arjun Singh Yadav, Bhupendra Singh Reniwal, Ankur Beohar
Portable and battery-operated electronics devices are in huge demand. An XOR/XNOR is the most prominent components of an arithmetic and logic unit (ALU) used for performing algebraic and Boolean operations in high-performance microprocessors used in Internet of Things (IoT). The XOR gates are part of critical devices such as adders, multipliers, multiplexers, and comparators, which influence the overall performance of microprocessors [1–3]. Further, portable device like IoT have four basic parts data processing unit, sensors/devices, connectivity, and user interface. The data processing unit contains the XOR gate circuit for basic operations such as addition, subtraction, comparison, and parity check. The portable IoT device must be small in size, consume low power, and offer high-speed [4]. The performance of the IoT device depends on data processing units that can be improved by the XOR gate design. As of now, mostly, the portable devices sink energy from the battery in the standby mode condition. Therefore, researchers developed several efforts to optimize the performance of XOR gates for IoT and embedded systems.
A novel efficient coplanar QCA full adder and full subtractor design
Published in International Journal of Electronics, 2023
Radhouane Laajimi, Lamjed Touil, Ali Newaz Bahar
An XOR gate is an important device in several designs of digital circuits, including the following arithmetic circuits and parity bit generator circuit. In the literature, many 3-Input gates have been developed (Ahmad et al., 2016; Bahar et al., 2017; Bahar & Wahid, 2019; Balali et al., 2017; Laajimi, 2018; Safoev & Jeon, 2020; Singh et al., 2016) with increased complexity and low density. Therefore, 3-Input and 2-Input QCA logic XOR components are proposed with a small number of cells and requires less area, especially 3-input exclusive OR gates given by (Laajimi, 2018) which is characterised by significant area and complexity. For this reason, a new FAS is proposed requiring fewer cells, less area and latency.