China
Africa
Explore chapters and articles related to this topic
PLL Circuits
Published in Wai-Kai Chen, Analog and VLSI Circuits, 2018
Muh-Tian Shiue, Chomg-Kuang Wang
Relaxation oscillators are the most commonly used oscillator configuration in monolithic IC design because they can operate in a wide frequency range with a minimum number of external components. According to the mechanism of the oscillator topology employed, relaxation oscillators can be further categorized into three types: (1) grounded capacitor VCO [20], (2) emitter-coupled VCO, and (3) delay-based ring VCO [21]. The operation of the first two oscillators are similar in the sense that the time duration spent in each state is determined by the timing components and the charge/discharge currents. The ring oscillator is one of the relaxation oscillators and has received considerable attentions recently in high frequency PLL applications for clock synchronization and timing recovery. Because the ring oscillator can provide high frequency oscillation with simple digital-like circuits that are compatible with digital technology, it is suitable for VLSI implementations.
Frequency Synthesizer
Published in Kaixue Ma, Kiat Seng Yeo, Low-Power Wireless Communication Circuits and Systems, 2018
Nagarajan Mahalingam, Kaixue Ma, Kiat Seng Yeo
The ring oscillator is the simplest of oscillators formed by connecting chain of gain stages in the positive feedback configuration. A simple inverter can function as a ring oscillator as shown in Fig. 13.11. The main advantage of the ring oscillator is its small size due to the absence of any passive devices and it is easier to implement in standard CMOS technology In additiont the ring oscillators can achieve a very large frequency tuning range. One of the major drawbacks in the ring oscillator is the poor phase noise in comparison to the LC-based oscillators. Alsot the maximum frequency of oscillation of the ring oscillator is limited as it is inversely proportional on the RC delay in the feedback chain. Thereforet the ring oscillator is not quite often used in high-frequency high-performance applications and is limited to frequency applications less than few tens of GHz. Hencet the following discussions in this section will be based on the LC oscillators as they are typically used in high-frequency wireless communication systems.
*
Published in Thomas Noulis, Noise Coupling in System-on-Chip, 2018
Thomas Noulis, Peter Baumgartner
An 11 stage CMOS CML differential ring oscillator [18] was designed and implemented in silicon. The process selected was a 28 nm CMOS, and the RF devices of the respective process design kit were used. A ring oscillator is a device composed of an odd number of NOT gates (inverters) in a ring whose output oscillates between two voltage levels representing true and false. The inverters are attached in a chain and the output of the last inverter is fed back into the first. In a physical device, no gate can switch instantaneously. In a device fabricated with MOSFETs, the gate capacitance must be charged before current can flow between the source and the drain. Thus, the output of every inverter in a ring oscillator changes a finite amount of time after the input has changed. Adding more inverters to the chain increases the total gate delay, reducing the frequency of oscillation [1,2].
Variation aware design of controlled voltage swing ring oscillator
Published in International Journal of Electronics, 2020
Abir J. Mondal, J. Talukdar, Bidyut K. Bhattacharyya
A ring oscillator is a closed loop chain of similar gates with a negative feedback to provide oscillation (Farahabadi, Naimi, & Ebrahimzadeh, 2009; Leung, 2002; Weiandt, 1998). The traditional ring oscillators (Hassan, Anis, & Elmasry, 2005; Mizuno et al., 1996) designed using MOS gates are shown in Figure 1. Figure 1(a) shows the differential design (Alioto, 2001; Docking & Sachdev, 2003) and Figure 1(b) shows single ended delay (Farahabadi et al., 2009) stage design. In Figure 1(a), even number of differential MCML stages is connected, where the last positive output is fed into the negative input of the first MCML. These are designed using MOS gates. The resistance, RL1 is also introduced using separate transistors, Mp as shown in Figure 1(a). The extra load capacitances at every output node of the delay stage are CL and are not the part of the device parasitic capacitance, Θ. In contrast, Figure 1(b) portrays a simple ring oscillator design using a single MOS gate with CL as the load capacitance. The resistance RL in Figure 1(b) is also controlled by a PMOS gate and a transistor Mn where the signal, Vin is applied. Several equations (Docking & Sachdev, 2003; Weiandt, 1998) exist to predict the frequency of oscillation of a ring oscillator. These equations differ due to various assumptions and simplifications made in the derivations. An accurate prediction reduces the design time and to do so manual calculations are taken up reflecting the simulations as well as portraying the trade-off among the performance parameters. Depending on the assumptions considered, the differential ring oscillator’s (Figure 1(a)) closed loop solution is given in Equations (1) and (2) (Alioto, 2001; Docking & Sachdev, 2003).