PoP

PoP

Package on package (PoP) refers to a technology where two or more functional chips, such as flash, DRAM, or digital processors, are stacked on top of each other within a single package. The top package uses wire bonding technology while the bottom one uses flip-chip technology. PoP allows for the integration of a high pin count digital logic processor in the bottom package and high capacity memory dies in the top package.From: Introduction to Microsystem Packaging Technology [2017], Modeling and Fabrication Aspects of Cu- and Carbon Nanotube-Based Through-Silicon Vias [2021]

Prospects for Microsystems Packaging Technology

View Chapter

Purchase Book

Published in Yufeng Jin, Zhiping Wang, Jing Chen, Introduction to Microsystem Packaging Technology, 2017

Yufeng Jin, Zhiping Wang, Jing Chen

(2) Package-on-Package (PoP)–Same and/or different functional chips (e.g., flash, DRAM, digital, etc.) may be stacked into one package using the mixed interconnection technology, i.e., the top package uses wire bonding technology while the bottom one uses flip-chip technology.

Modeling and Fabrication Aspects of Cu- and Carbon Nanotube-Based Through-Silicon Vias

View Article

Journal Information

Published in IETE Journal of Research, 2021

Tanu Goyal, Manoj Kumar Majumder, Brajesh Kumar Kaushik

The 3D integration is achieved using the following primary ways of packaging [4]: (1) PiP (Package-In-Package) and (2) PoP (Package-on-Package). The basic concept of PiP is similar to that of innovative stacked package. The finished PiP has the same form, fit, and function as a conventional FBGA (fine pitch ball grid array). PoP is a 3D package solution precipitously meant for portable devices owing to its flexibility, accuracy, and testability. This packaging technology is classified into two packages such as top and bottom. PoP integrates a high pin count digital logic processor in bottom package and high capacity memory dies in top package. For 3D ICs, new advanced interconnects have to be introduced, so as to meet the requirements of such ICs.

Explore chapters and articles related to this topic

Prospects for Microsystems Packaging Technology

Modeling and Fabrication Aspects of Cu- and Carbon Nanotube-Based Through-Silicon Vias