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Towards Multicores: Technology and Software Complexity
Published in Marcello Coppola, Miltos D. Grammatikakis, Riccardo Locatelli, Giuseppe Maruccia, Lorenzo Pieralisi, Design of Cost-Efficient Interconnect Processing Units, 2020
Marcello Coppola, Miltos D. Grammatikakis, Riccardo Locatelli, Giuseppe Maruccia, Lorenzo Pieralisi
Between Multicore homogeneous processors and Multicore SoCs, we can identify yet another category of products called Multicore heterogeneous processors. Similar to Multicore processors, these heterogeneous architectures decouple the host controlling core from a set of specialized processing cores and are designed to be relatively open in terms of supported applications (targeting at least a class of applications). Well-known examples include the Intel network processor, and the IBM, Sony and Toshiba Cell broadband engine that addresses mainly the video game market [158]. The Cell is a well-known general-purpose pipelined Graphics Processing Unit (GPU) which can perform real-time computing, as well as graphics processing. In a general sense it can be positioned in the gap between general purpose CPU(s) and specialized high-performance processors, such as traditional graphic processors. It is based on a single 64-bit PowerPC processor surrounded by eight identical SPE co-processors. Similar to the central PowerPC processor, each SPE (synergistic processing element) is a dual-issue machine, but unlike the PPE (parallel processing element) the two execution pipelines are not symmetrical. In other words, each SPE can execute two (different) instructions simultaneously. Instead of using a hierarchy of caches, each SPE has a local memory for audio, video and image processing.
Introduction
Published in Heqing Zhu, Data Plane Development Kit (DPDK), 2020
These systems are used for different scenarios; each hardware has certain advantages and disadvantages. For large-scale and fixed function systems, the hardware accelerator is preferred due to its high performance and low cost. The network processor provides the programmable packet processing, thereby striking a balance between flexibility and high performance, but the programming language is vendor specific. In the recent years, P4 has emerged as a new programming language for packet processing, and it gained the support from Barefoot Switch and/or FPGA silicon, but not common for NPU.
Recent Advances in Low-Power Design and Functional Coverification Automation from the Earliest System-Level Design Stages
Published in Christian Piguet, Low-Power Processors and Systems on Chips, 2018
Thierry J.-F. Omnés, Youcef Bouchebaba, Chidamber Kulkarni, Fabien Coelho
Network processors exploit task and packet level parallelism to achieve high throughput. To date, this has resulted in a huge diversity of architectures for similar applications. Driven by practical implementations. This section explores the different trade-offs in network processor design and implementation.
A scalable cloud-based cyberinfrastructure platform for bridge monitoring
Published in Structure and Infrastructure Engineering, 2019
Seongwoon Jeong, Rui Hou, Jerome P. Lynch, Hoon Sohn, Kincho H. Law
Cloud computing services are typically categorised into three service models (Mell & Grance, 2011): (1) Software as a Service (SaaS) that provides applications and web services to end users, (2) Platform as a Service (PaaS) that provides runtime and database supports and (3) Infrastructure as a Service (IaaS) that provides the basic computing utilities including network, processor and storage. As depicted in Figure 1, the cloud-based SHM cyberinfrastructure platform acts as PaaS and SaaS that utilise the computing infrastructures and platforms (i.e. IaaS and PaaS) for hosting the data management and application services.