China
Africa
Explore chapters and articles related to this topic
Boolean Algebra and Logic Gates
Published in Dale Patrick, Stephen Fardo, Vigyan ‘Vigs’ Chandra, Electronic Digital System Fundamentals, 2020
Dale Patrick, Stephen Fardo, Vigyan ‘Vigs’ Chandra
NAND gates can be used to produce an OR function. Figure 3-25 shows how NAND gates are connected to achieve the OR function. Each input is applied to a NOT gate. The NOT function is achieved by a NAND gate with its inputs connected together. The A and B inputs then become Ā and B¯. This is applied to a two-input NAND gate. The output of this gate then becomes (AB¯). DeMorgan’s law must be applied to the expression for it to be meaningful. To apply DeMorgan’s law, change the sign of the operator, complement each variable, and then complement the entire expression. This will produce an output of A + B, which is the OR function. Figure 3-25 shows the steps needed to apply DeMorgan’s law to the output of the gate circuit. Since the output of this gate circuit is A + B, we have shown that NAND gates can be used to achieve the OR function.
Digital theory, logic, and two-state control
Published in Raymond F. Gardner, Introduction to Plant Automation and Controls, 2020
NAND and the NOR gates are considered universal gates, because all other gates can be constructed from combinations of either of them. Although either would work, the NAND gate is preferred for constructing electronics-based gates. The electronics for the NAND circuit is faster and more efficient than the NOR circuits for several reasons. First, it can handle more than two inputs into a single transistor, so fewer transistors may be required. Additionally, the NAND gate uses a different crystalline structure that contributes to faster speed while also having off-states that have less gate leakage current. The better NAND-gate characteristics come from its NMOS construction, which relies on electron movement, whereas the NOR gate has a PMOS structure that relies on the movement of much-slower holes. These features result in faster speed, higher efficiency, and less heat generation. NAND gates are more advantageous for integrated circuits in terms of size, speed, and thermal reasons.
Basic Elements of Digital Circuits
Published in Nassir H. Sabah, Electronics, 2017
Logic gates are electronic circuits that perform some logic, or related, function. The main types of logic gates are shown in Table 12.2.1 together with their symbols, the operations they perform, and the corresponding truth tables. The inverter performs logic negation, which is denoted as usual by a bubble. Conjunction and disjunction are performed by AND gates and OR gates, respectively. A NAND gate is an AND gate with inverted output and is logically equivalent to an AND gate followed by an inverter; similarly for a NOR gate. The Exclusive-OR (XOR) gate differs from an OR gate, which is sometimes referred to as inclusive-OR gate, in that when all of its input are 1, the output is zero. The XOR operation is denoted by a circled plus sign. Although it can be implemented using the aforementioned gates (Exercise 12.2.1), the XOR gate is encountered in many important operations (Example 12.1.1), so that it is convenient to show it as a separate gate. If its output is inverted, the XOR gate becomes an exclusive-NOR (XNOR) gate. The transmission gate was discussed in Section 5.5, Chapter 5. When the control input C is 1, the gate input A is transmitted to the output. But when C is 0, both transistors of the gate are off, and the gate output is floating, that is, it has a high impedance to ground and will appear as an open circuit to whatever is connected to the output. The transmission gate is therefore useful for connecting together and disconnecting subcircuits of a system. An output that can have a high-impedance state, in addition to high and low, is referred to as tristate.
120 Gb/s all-optical NAND logic gate using reflective semiconductor optical amplifiers
Published in Journal of Modern Optics, 2020
The NAND logic gate produces ‘1’ output only if any of its inputs are ‘0’; thus NAND gate is the invert of an AND gate. The NAND schematic diagram and its corresponding truth table using the dual-RSOAs-based scheme are shown in Figure 2.