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Towards Multicores: Technology and Software Complexity
Published in Marcello Coppola, Miltos D. Grammatikakis, Riccardo Locatelli, Giuseppe Maruccia, Lorenzo Pieralisi, Design of Cost-Efficient Interconnect Processing Units, 2020
Marcello Coppola, Miltos D. Grammatikakis, Riccardo Locatelli, Giuseppe Maruccia, Lorenzo Pieralisi
Static power can also be controlled using a number of complex techniques. Multi-threshold CMOS design (called power gating) scales down the supply and scales up threshold voltage to meet power vs. performance tradeoffs. Since scaling down threshold voltage, exponentially increases sub-threshold leakage, so-called sleep transistors with high threshold voltage are inserted to function units or gates. Sleep transistors are turned off during the sleep mode, which can significantly reduce the leakage. Moreover, multiple supply and threshold voltages takes advantage of the fact that independently optimizing different parts of the design is likely to result in different values for the optimum supply and threshold voltages for each macro-level block or standard cell (called voltage islands).
Design and Simulation of Reliable Low Power CMOS Logic Gates
Published in IETE Journal of Research, 2023
The main controlling parameter at circuit-level design is threshold voltage of the MOS device. The large threshold voltage helps to reduce leakage current but degrades the performance of the MOS device. Therefore, multi-threshold CMOS (MTCMOS) technique provides the balance between low and high threshold voltages for MOS devices. Extra high threshold sleep transistors are used in MTCMOS technique as the header and/or footer. Sleep transistor/s is/are turned off during the standby time, while these are turned on in active mode of the logic circuits [7,8].
A Novel Design of Low Power & High Speed FinFET Based Binary and Ternary SRAM and 4*4 SRAM Array
Published in IETE Journal of Research, 2023
N. Shylashree, M. S. Amulya, Gulur R. Disha, N. Praveena, Vijay Kumar Verma, S. Muthumanickam, V. Kannagi, K. Sivachandar, Vijay Nath
Multi-Threshold CMOS are circuits where an extra pair of high threshold voltage (Vt) sleep transistors are fitted at Supply voltage (Vdd) and ground to reduce power consumption while Low threshold voltage (Vt) transistors are used to reduce the delay [2–4].