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Computer memory systems
Published in Joseph D. Dumas, Computer Architecture, 2016
Given the desired main memory size in most computer systems as compared to the amount of DRAM that can be fabricated on a single integrated circuit, DRAM is not usually sold as individual chips. Rather, several integrated circuits (ICs) are packaged together on a small printed circuit board module that plugs into the system board, or motherboard. These modules come in various forms, the most popular of which are known as dual inline memory modules (DIMMs) and small outline dual inline memory modules (SODIMMs). Some of these modules are faster (have lower access times and/or higher synchronous clock frequencies) than others, and different types plug into different size sockets (thus, it is important to buy the correct type for a given system), but they all use DRAM devices as the basic storage medium.
The PC
Published in Mike Tooley, PC Based Instrumentation and Control, 2013
In many cases you can fit a memory module rated at the same speed or faster than that at which a PC's memory system is rated. This means that you should be able to replace a 70 ns module with one rated at either 70 or 60 ns but not one rated at 80 ns. It is, however, worth noting that some older systems check the module speed at boot-up and will only accept a module that has the same speed rating as that of the system to which it is fitted. This explains why some systems will refuse to accept faster memory modules than those being replaced!
Force-System Resultants and Equilibrium
Published in Richard C. Dorf, The Engineering Handbook, 2018
A RAM system is implemented using memory devices such as SRAM (static RAM) and DRAM (dynamic RAM). Early systems used individual SRAM-or DRAM-integrated circuit chips in dual inline packages (DIP) directly in implementing the memory system. Nowadays, memory devices are packaged as industry-standard modules such as SIMMs (single inline memory modules) and DIMMs (dual inline memory modules). Memory modules consist of several memory chips assembled on a single standardized small circuit board, thereby easing implementation and increasing reliability.
Power-Aware Characteristics of Matrix Operations on Multicores
Published in Applied Artificial Intelligence, 2021
Guruprasad Konnurmath, Satyadhyan Chickerur
TensorFlow engine performs activity of dynamic resource management system (DRMS) by generating graph nodes. Nodes of the graph are represented by the mathematical operations and the edges in the graph communicating between these nodes represent multidimensional arrays called as tensors. This flexible and adaptive architecture of TensorFlow allows distributing computations on one or more CPU as well GPU in par with the requirement. Representing itself as a graph, an efficient data structure TensorFlow allows boosting execution speed. Whenever, the unused nodes in the graph are detected and eliminated, thus optimizing it for size and evacuating idle power consumption. It also identifies redundant operations or sub-optimal graphs and replaces them with the best alternatives with the aim of optimizing time constraints. This nature of TensorFlow ensures computation optimization yielding efficiency in terms of execution time as well as power consumption. In the proposed work, TensorFlow library is used to run matrix operation on particular device instead of automatic selection using tf.device to create a dedicated device context and all the related operations around the context shall execute on the same designated device. Since integrated GPU does not own video Random Access Memory, this integrated GPU requires only a minimal amount of memory space. In comparison with onboard-graphics card consist of its own video memory module, or a short Video Random Access Memory, which is found to be one of the biggest advantage. Also for these dedicated graphics card, peripheral, and external devices are clocked in faster way leading to high-performance level. This huge performance throughput is accompanied with higher power consumption, heat dissipation and which lead to memory fragmentation in some cases. TensorFlow library in the proposed work is used to select the dedicated devices and to limit memory growth.
A comparative study between PCR, PLSR, and LW-PLS on the predictive performance at different data splitting ratios
Published in Chemical Engineering Communications, 2022
The simulations for this work were operated using the computer configuration specifications such that Central processing unit model: Intel Core i5-4210U operating at a base frequency of 1.70 Ghz (2 cores 4 threads), Random-access memory: 12 Gigabytes Double Data Rate 3L Cycles 11 (small outline dual in-line memory module), Operating System: Windows 8.1 64-bit, and MATLAB version R2019b. All simulations were done on the same system to affirm the consistency of the results.