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2D Materials for Spin Orbital Torque MRAM
Published in Shubham Tayal, Abhishek Kumar Upadhyay, Deepak Kumar, Shiromani Balmukund Rahi, Emerging Low-Power Semiconductor Devices, 2023
M Shashidhara, Abhishek Acharya
Several nonvolatile memory architectures have been invented in recent years and are undergoing extensive development and research [9]. There is no unique data storage device that can today meet all of the requirements simultaneously. Combining several memory architectures in a single computational system is a time-consuming and difficult task. It also has a negative impact on the system’s overall performance. As a result, there is great interest in finding versatile memory architecture that has high storage density and nonvolatile memory, low latency, and high endurance. Many alternative memory technologies have been offered as potential versatile memories in recent decades. Resistive random-access memory (RRAM), phase change memory, racetrack memory [10], and magneto resistance random-access memory (MRAM) are some of the most well-known alternate memories. In MRAM, the magnetic state of a nanometer-scale magnet is used to store information. The magnetic tunnel junction (MTJ) is a fundamental storage element in MRAM.
Simulation of Multilayer Atom Nanostructures for Spinmechatronics
Published in Satya Bir Singh, Prabhat Ranjan, Alexander V. Vakhrushev, A. K. Haghi, Mechatronic Systems Design and Solid Materials, 2021
A. V. Vakhrushev, A. Yu. Fedotov, V. I. Boian, A. S. Sidorenko
Over the past decade, a new direction of research has been formed [11, 12], in which materials under the influence of external electric and magnetic fields are able to change the electrical resistance by several orders of magnitude. This phenomenon has received the name of colossal magnetic resistance and has significant prospects for creating new technologies for recording and storing information with increased density and low power consumption compared to conventional modern data carriers. The study of a crystalline sample of manganite of perovskite structure by the method of built-in combination of a scanning tunneling microscope and an electron microscope revealed a distortion of the crystal lattice of a substance caused by the combined motion of electrons and phonons. Materials with colossal magnetic resistance can be used to create computer non-volatile memory (MRAM), as well as in other spintronics and electronics devices.
Spin-Transfer-Torque MRAM
Published in Xiaobin Wang, Krzysztof Iniewski, Metallic Spintronic Devices, 2017
Recently, technologists started developing more advanced spintronic devices built on a semiconductor integrated circuit (IC) platform. A widely publicized device is magnetoresistive random access memory (MRAM). The first MRAM product was commercialized in 2006 by EverSpin Technologies (then as part of Freescale Semiconductor) [5]. While the memory capacity was small (4 Mbits) and the IC was based on a legacy 180 nm complementary metal oxide semiconductor (CMOS) platform, the enabling technology (Toggle MRAM [6, 7]) was regarded as a remarkable by-product of fundamental nanomagnetism, sophisticated MTJ engineering, and tailored circuit design. Until now, however, the commercially available Toggle MRAM has not made the impact originally anticipated. Drawbacks pertaining to this first-generation MRAM are well understood, limiting its application to a niche market.
Neural network detector with sparse codes for spin transfer torque magnetic random access memory
Published in Cogent Engineering, 2023
Spin transfer torque magnetic random access memory (STT-MRAM) is one of the most promising technologies for next-generation non-volatile memory (NVM) systems. Flash and dynamic RAM (DRAM) are now leading in electronic memory. However, the problem of the write/erase (W/E) cycles is hugely challenging for Flash systems. The reliability of the device is significantly degraded due to the W/E being over the limit. Moreover, DRAM cannot provide a non-volatile feature and has high power consumption due to the significant effect of inevitable leakage current. The STT-MRAM has arrived as a leading candidate for stand-alone and embedded NVM applications among various emerging NVM technologies (H. Cai et al., 2021). Significantly, due to attractive advances such as durable and non-volatile devices or nanosecond read and write processes, the STT-MRAM is very useful in many applications, such as consumer electronics devices, cache in mobile devices, and IoT/AI devices.
Electric field induced magnetization reversal in magnet/insulator nanoheterostructure
Published in International Journal of Smart and Nano Materials, 2020
Qihua Gong, Min Yi, Bai-Xiang Xu
Nowadays magnetic storage plays a critical role in the development of fast, high-density, nonvolatile memory technology [1]. The typical example is magnetic random access memory (MRAM) device which relies on the magnetic tunneling junction (MTJ) to storage bit information. MTJ is usually constituted of insulator, free magnetic layer in which the magnetization can be switched by an external field, and fixed magnetic layer in which the magnetization direction is firmly pinned. For example, if the configuration of magnetization in the free layer antiparallel to that in the fixed layer represents bit ’0ʹ, switching the magnetization in the free layer during the writing process to achieve a parallel configuration leads to bit ’1ʹ. A huge number of MTJ units realize the information storage. The writing in MTJ is intrinsically a magnetization reversal process in the free layer. Therefore, developing new strategies to switch magnetization in the free layer is indispensable for revolutionizing spintronics.
Hybrid buffers based coarse-grained power gated network on chip router microarchitecture
Published in International Journal of Electronics, 2020
Yogendra Gupta, Lava Bhargava, Ashish Sharma, M.S. Gaur
The hybrid design focus to maximize the advantages of emerging memory technologies for performance improvement with the same power budget. STT-MRAM has a higher density that inspires to incorporate greater buffer memory space as compared to SRAM under the same area constraint. We have seen already the effect of the virtual channels on the network performance. It boosts overall network performance with no additional area overheads. We took this hybrid buffer architecture from the literature ‘(Jang et al., 2012)’. Figure 9 represents the hybrid input buffer of a Virtual Channel. Compared to the pure SRAM buffer the STT-MRAM is attached to each Virtual Channel in parallel with the SRAM buffer. The First In First Out (FIFO) buffer control the ‘read/write’ pointer. Write pointer is pointing to SRAM buffer only because whenever a flit comes it first written into the SRAM buffer. The read buffer covers the entire buffer entries because the outgoing flit can depart either from STT-MRAM or SARM. The migration controller tracks the flit activity and relocate the flit from STT-MRAM to SRAM. We have used the power efficient ‘lazy migration’ scheme ‘(Jang et al., 2012)’.