China
Africa
Explore chapters and articles related to this topic
CAD Tools and Design Kits
Published in John D. Cressler, Measurement and Modeling of Silicon Heterestructure Devices, 2018
In addition to device design, programmable cells may be created to assist in sound layout practices for silicon germanium technologies. These include the formation and properties of noise-isolating moat structures, guard rings, substrate contact techniques to achieve optimum device matching, and prevention of electromigration failure and voltage drops through proper metallization. Isolation moats place a region of high resistance between two circuits, or separate areas of the chip, to reduce noise or signal coupling through the substrate. Guard rings form a barrier to the input of ionic contaminants, which are highly mobile in silicon dioxide, by surrounding the device or the die with a wall of metal. The contacts of the isolation guard ring may be switched off or sections may be removed for chaining of devices. Substrate contacts maintain the substrate potential to the desired voltage levels and assure that local potential variations are minimized to prevent latch-up, especially in highly resistive substrates. In the layout, good matching can be attained by keeping like devices close together or adjacent, placing groups of devices around a common center, orienting devices in the same direction, or using identical layouts. Abutment of MOSFET devices allows for devices to be merged into a single diffusion.
Physical Design of MOS Integrated Circuits
Published in Tertulien Ndjountche, CMOS Analog Integrated Circuits, 2017
In CMOS circuits in which a thyristor consisting of parasitic npn and pnp bipolar transistors, Qn and Qp, (see Figure 3.17) are formed, a latch-up effect can occur [5]. The parasitic circuit includes the substrate and well resistors, rs and rw, and a positive feedback is formed around Qn and Qp. Due to transient noises, one of the two transistors can become forward biased and feeds the base of the other transistor. As a result, a current flows between the supply voltage lines and the circuit is unable to deliver a response to an input signal. Provided the feedback gain is greater than or equal to unity, this current will increase until the circuit burns out.
Electronics Requirements for Collider Physics Experiments
Published in John D. Cressler, H. Alan Mantooth, Extreme Environment Electronics, 2017
One must also be concerned about instantaneous disruption of electronic devices. Even though these disruptions are most common with highly ionizing ion radiation, even singly charged minimum ionizing particles can cause disruption. This is especially true as device sizes shrink and the charge required to change state is reduced. Latchup can be a catastrophic failure and must be avoided at all costs by device design and layout. Single even upsets (SEU) that cause bit flips, which can be restored by re-writing, can be problematic but possibly manageable. Since mitigation techniques for SEUs typically cost power or chip real estate or both, it is usually desirable to evaluate the severity to overall system performance of a particular bit-flip error in order to decide what kind of mitigation technique, if any, to employ.
A simple and versatile overcurrent protection circuit for power MOSFETs
Published in International Journal of Electronics, 2019
Praveen V. Pol, Sanjaykumar L. Patil, Sanjeev Kumar Pandey
In the above two modes, the OCP circuit operates independently and the role of the fault signal FS is simply to report the fault condition but it is not essential. In this type of mode the OCP circuit protects the MOSFET from overcurrent, however the single cycle latch-up action is executed by the micro-controller on the reception of the fault signal FS from the OCP circuit. The generation of the input signal or PWM pulses is discontinued indefinitely untill the micro-controller is not reset. Shutdown time is insignificant in this mode. By programming the micro-controller and using the OCP FS output, the cycle-by-cycle shutdown or multiple cycle shutdown mode is converted into a single cycle latch-up mode. The input and output waveforms in this mode are shown in Figure 8. It is observed that under the fault condition the driver IC output is shutdown and input signal is discontinued. Hence both, and remains low.
A Comprehensive Review on Level 2 Charging System for Electric Vehicles
Published in Smart Science, 2018
Saadullah Khan, Samir Shariff, Aqueel Ahmad, Mohammad Saad Alam
The function of the EVSE is performed via several high power relays that are in the power path. In order to safely operate these relays, sufficient drivers with adequate protection circuitry must be used:an overcurrent relay for overloads and short circuits protectiona contactor switch is used to latch up the supply to the connector and also keep the connection de-energized when not plugged ina controller circuit that interfaces with the vehicle’s onboard charging system and serves ground fault protection; it may also have some power metering capabilities as wellindicators and displays on the exterior to provide status and alarm information and guide the user through the operational sequencea cable that connects the EVSE to the charging receptacle on the vehicleThe conductive connector that plugs into the vehicle.
A Low Power CMOS UWB LNA with Dual-band Notch Filter Using Forward Body Biasing
Published in IETE Journal of Research, 2020
Maryam Babasafari, Mostafa Yargholi
In a long-channel enhancement mode n-MOSFET, where body, source, and drain terminals are connected to ground; suppose that an external voltage is connected to the gate terminal, which is initially zero. As the gate-source voltage (VGS) becomes positive, the hole in the P-substrate is repelled from the gate area, leaving negative ions behind, so as to mirror the charge on the gate. In other words, a depletion region is created. In this situation, no current flows; because, no charge carries are established. When the gate-source voltage increases, the width of the depletion region and the potential reaches a adequately positive value, thus the electrons flow from the source to the interface and finally to the drain [6]. The main problem with a low voltage design is the restriction of the threshold voltage (Vth), since it is not expected to reduce much lower what is existing today [12]. Forward body biasing technique is announced to solve this restriction problem and further reduce Vth. Besides, for a standard CMOS technology without the multiple gate-oxide options, the threshold voltage can be manipulated by the DC biasing at the body terminal, adding one more degree of freedom in the circuit design. Typically, the threshold voltage of channel MOSFET can be defined as [6]: where Vbs is the body-source voltage, Vth0 is the threshold voltage for Vbs =0, γ is a process dependent parameter, and finally φf is a semiconductor parameter with a typical value in the range of 0.3–0.4 V [6]. According to the above equation, increasing the Vbs can reduce the Vth, which can reduce the power supply and power consumption [6,13,14]. It is noted that, as the forward body bias turns on the source to body connection of the MOSFET, a DC current flows across the junction with an exponential dependence on the body voltage, leading to extra power dissipation and possibly latch-up failure. To avoid the excessive junction conduction, a current-limiting resistor, Rb, attendant with a parallel capacitor at the body terminal. It could be simply found that the large bias resistor leads to little noise figure. The general model of the small signal of the cascode topology with noise sources is demonstrated in Figure 5. Four sources of noise have been considered: the thermal noise of source resistance (in,Rs), the thermal noise of the channel current (in,d), the gate-induced current noise (in,g) and the thermal noise of the output resistance (in,out).