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Electromagnetic Compatibility for High-Speed Circuits
Published in Xing-Chang Wei, Modeling and Design of Electromagnetic Compatibility for High-Speed Printed Circuit Boards and Packaging, 2017
The 3D integration consists of 3D IC packaging, 3D IC integration, and 3D silicon integration [9]. Among all those 3D integrations, TSV-based interposer (passive and active) is preferred by industries due to its easy fabrication and good heat dissipation. Figure 1.6 shows a typical TSV-based interposer. The interposer is a silicon substrate inserted between the die stack and the second-level package. It serves as a space transformer through redistribution by connecting the fine-pitch microbumps to the coarser-pitch C4 bumps [1]. Redistribution layer (RDL) is the metal layer on the top and bottom of the interposer. It is used for the horizontal interconnection, and TSV is used for the vertical interconnection.
A New Class of High-Capacity, Resource-Rich Field-Programmable Gate Arrays Enabled by Three- Dimensional Integration Chip-Stacked Silicon Interconnect Technology
Published in Katsuyuki Sakuma, Krzysztof Iniewski, 3D Integration in VLSI Circuits, 2018
Suresh Ramalingam, Henley Liu, Myongseob Kim, Boon Ang, Woon-Seong Kwon, Tom Lee, Susan Wu, Jonathan Chang, Ephrem Wu, Xin Wu, Liam Madden
Being originally developed for use in a variety of die-stacking design methodologies, silicon interposers provide modular design flexibility and high-performance integration suitable for a wide range of applications. The silicon interposer acts as a sort of microcircuit board in silicon on which multiple dies are set side by side and interconnected. Compared to organic or ceramic substrates, silicon interposers offer far finer interconnect geometries (approximately 20X denser wire pitch) to provide device-scale interconnect hierarchy that enables more than 10,000 die-to-die connections.
Improving the washability of smart textiles: influence of different washing conditions on textile integrated conductor tracks
Published in The Journal of The Textile Institute, 2020
Sigrid Rotzler, Christine Kallmayer, Christian Dils, Malte von Krshiwoblozki, Ulrich Bauer, Martin Schneider-Ramelow
The layout of the test samples consists of two separate parallel conductor tracks with different strain scenarios (Figure 3): curves, corners and track segments that both run with the weft and the warp direction of the textile substrates. To simulate the mechanical strain of non-flexible components, a dummy interposer (FR-4 blank, 1 mm), surrounded by a thermoplastic polyurethane (TPU) dam and encapsulated in TPU resin, is added to the layout.