China
Africa
Explore chapters and articles related to this topic
Dynamic Random Access Memory (DRAM)
Published in Shimeng Yu, Semiconductor Memory Devices and Circuits, 2022
What makes HBM attractive is not only the higher integration density (multiple dies on the same 2D form factor), but also the wide I/O interface that it could offer. As aforementioned, the DDR/LPDDR often has a 64-bit-wide I/O interface, and GDDR often has a 32-bit-wide I/O interface. Now, HBM offers a 1024-bit-wide I/O interface. Even running at a slower I/O clock frequency, which means lower interface speed (Gbps) per pin, HBM could offer a significantly higher bandwidth (GB/s) at the system level. Table 3.1 summarizes the evolution of HBM interface protocol standard and the comparison with LPDDR and GDDR counterparts. As of 2020, HBM has gone through three generations (HBM, HBM2, and HBM2E). The capacity per DRAM die has increased from 2 Gb to 16 Gb, and the number of DRAM dies in the stack has increased from 4 to 8; thus, the total capacity has increased from 1 GB to 16 GB. The system bandwidth has increased from 128 GB/s to 410 GB/s. As a comparison, LPDDR5 and GDDR6 offer the system bandwidth 37.5 GB/s and 56 GB/s.
Case Studies
Published in Lambrechts Wynand, Sinha Saurabh, Abdallah Jassem, Prinsloo Jaco, Extending Moore’s Law through Advanced Semiconductor Design and Processing Techniques, 2018
Lambrechts Wynand, Sinha Saurabh
Its latest offering, announced in 2017 and planned to be mass-produced in 2018, is the Volta line of GPUs, a processing unit based on a 12 nm FinFET technology node, housing 21 billion transistors in its main processing core on a die size of 815 mm2 (Nvidia 2017). Its predecessor, the Pascal line of GPUs, was built on a 14 nm technology and contained 15 billion transistors on a die size of 610 mm2 on its primary processing core. Huang additionally said, during this keynote address, that the Volta GPU is at the limits of photolithography, therefore acknowledging that this process step (photolithography) is the primary challenge to adhering to Moore’s law. The Volta line of GPUs has a redesigned microprocessor architecture with respect to the Pascal line, and is able to operate 50% more efficiently than its predecessor. In addition, these GPUs implement high bandwidth memory (HBM) for their video RAM (VRAM), as opposed to the traditional, albeit less costly, double data rate (DDR) memory – currently type 5, GDDR5 (Nvidia 2017). HBM uses vertically stacked dynamic RAM (DRAM) memory chips interconnected by through-silicon vias, shortening the path between individual memory chips, effectively reducing power consumption, reducing the required area and allowing for higher bandwidth at lower clock speeds.
Quest for Energy Efficiency in Digital Signal Processing
Published in Tomasz Wojcicki, Krzysztof Iniewski, VLSI: Circuits for Emerging Applications, 2017
Ramakrishnan Venkatasubramanian
A standard that leverages Wide IO and TSV technologies to deliver products with memory interface ranging from 128 GB/s to 256 GB/s has been defined by the HBM initiative by JEDEC standard in March 2011 [23]. The HBM task group is defining support for up to 8-high TSV stacks of memory on a data interface that is 1024-bit wide. HBM provides very large memory bandwidth because of parallelism; it basically integrates memory into the same SoC package and thus increases processing capacity in the SoC and reduces the power per Gbps compared to HMC.
Challenges in Design, Data Placement, Migration and Power-Performance Trade-offs in DRAM-NVM-based Hybrid Memory Systems
Published in IETE Technical Review, 2023
Sadhana Rai, Basavaraj Talawar
Implementations of hybrid memory have used either DRAM alternatives such as High-Bandwidth Memory (HBM) or Hybrid Memory Cubes (HMC) developed using 3D-stacked technology [32,33] or NVM devices. In the case of mobile devices, alternatives like LPDDR and WideIO2 are used to operate within the power and bandwidth constraints [34]. These technologies provide higher bandwidth and better energy efficiency (LPDDR: 30–50% [33]), when compared to conventional DRAM. Integration of HBM-DDR4 provides acceptable efficiency, and it depends on cache hit rate [33]. NVM technologies successfully integrated into Hybrid memory systems are Phase Change Memory (PCM), Spin Transfer Torque RAM (STT RAM), Resistive RAM(Re-RAM) and 3D-XPOINT. Table 1 gives the details about different NVM devices and Table 2 gives details of devices that have emerged as alternatives to DRAM. STT-RAM is a variant of Magnetic RAM (MRAM) that has better load latency when compared to DRAM [44]. STT-RAM and ReRAM are also considered to be good emerging technologies in NVM because of the operational benefits they provide, but they suffer from low density and they are less mature when compared to other NVMs [45]. However, STT-RAM is considered as a potential candidate for processor cache because of its read latency and good write endurance when compared to other NVMs [44]. In our study, we found that various NVMs that have been used are STT-RAM (≈ 4%), 3D-XPoint (12.5%), ReRAM (≈ 2%), PCM (75%). PCM is used widely because of the benefits it provides, such as (1) higher bit density, (2) the cost per bit of PCM is much lower than DRAM and (3) lower leakage power. Moreover commercial availability of PCM-based devices has attracted many researchers to include PCM as non-volatile memory in hybrid memory [2,9,15,45–47].