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Dynamic Random Access Memory (DRAM)
Published in Shimeng Yu, Semiconductor Memory Devices and Circuits, 2022
As aforementioned, DRAM has faced fundamental challenges in 2D scaling due to the requirements of higher aspect ratio (that is lithography and etching demanding) and higher-k dielectric (while maintaining leakage current low). It is thus necessary to seek an alternative approach to improve the DRAM’s performance at the system level. One promising approach is to explore the third dimension by staking multiple 2D DRAM dies to further increase the integration density and potentially boost the I/O bandwidth. The technology enablement for such 3D integration of multiple dies is the through-silicon-via (TSV). TSV is able to make a metallic conductive via through the silicon wafer (or die) that is thinned to several tens of μm to connect the front side interconnect and the back side interconnect. Figure 3.26 shows the typical fabrication process flow of the TSV: (1) deep trench is etched into silicon; (2) isolation dielectric is deposited covering the trench; (3) copper diffusion barrier and adhesion layer are deposited covering the trench; (4) copper is electroplated to fill in the trench; (5) silicon surface is planarized to remove residual copper by chemical-mechanical-polishing (CMP); (6) wafer/die thickness is shrunk by grinding. Figure 3.26(b) summarizes the typical TSV parameters. In general, the TSV pitch range is 10 μm–50 μm; the TSV diameters range is 5 μm–25 μm; the TSV aspect ratio range is 5–20; the TSV resistance range is 0.01–0.1 Ω; the TSV capacitance range is 50 fF–500 fF.
Mechanically Flexible Interconnects and TSVs
Published in Vikas Choudhary, Krzysztof Iniewski, MEMS, 2017
Hyung Suk Yang, Paragkumar Thadesar, Chaoqi Zhang, Muhannad Bakir
A TSV generally consists of a metal conductor in vertical direction through silicon and thin dielectric liner between the metal and the silicon. Various materials such as copper, tungsten, nickel, and aluminum can be used as metal in TSVs. Copper is mostly used for the TSV metal part because of the ease of fabricating high-aspect ratio TSVs in chips as well as in silicon interposer packages using electroplating, better electromigration resistance, and comparatively lower resistivity. But CTE of copper is almost seven times higher than that of silicon. This induces higher stress in silicon surrounding the copper as well as causes reliability issues for the TSV structure when thermal load is exerted on TSVs. Moreover, the previous section discusses the significant effect stress has on the performance of MEMS devices.
Electromagnetic Compatibility for High-Speed Circuits
Published in Xing-Chang Wei, Modeling and Design of Electromagnetic Compatibility for High-Speed Printed Circuit Boards and Packaging, 2017
For the future development of the semiconductor industry, ITRS lays out a research and development plan on more-than-Moore strategy. Various packages have been developed toward the high-density integration. In particular, a three-dimensional (3D) structure with a TSV technology has emerged as a viable solution for more-than-Moore strategy [7,8]. Unlike the traditional two-dimensional (2D) layouts of the devices inside a chip, 3D IC integration is characterized as a system-level architecture, in which multiple layers of planar devices are stacked and interconnected using TSVs in the vertical direction. A TSV is a coated metal via residing in a silicon substrate for vertical interconnection between stacked dies. The transform from 2D IC integration to 3D IC integration is just like that in a modern city: individual houses are replaced by high-rise buildings in order to achieve more living space. The TSVs, just like the lifts used in those high-rise building, provide fast and efficient electrical connections between different layers of 3D ICs.
High-Performance 3D Mesh-Based NOC Architecture Using Node-Layer Clustering
Published in IETE Journal of Research, 2023
Navid Habibi, M. Reza Salehnamadi, Ahmad Khademzadeh
A topology in a network is also defined as how nodes connect. The usual topologies are two-dimensional (2D) or three-dimensional (3D) [6]. The 3D types are endowed with many advantages compared with 2D topologies including short connections, which would lead them to have lower latency development as well as lower levels of energy/power consumption. 3D integrated circuits (ICs) also have many advantages and are constructed by numerous 2D layers connected in vertical connections to through-silicon via (TSV). There are several requirements to design 3D NOC architectures. In this respect, network complexity is an important parameter mentioned in router types and links. Link length of the network should be also short and in the same size. The network diameter can even affect its performance. Latency and network energy consumption are accordingly factors mentioned in architecture design. Moreover, reliability and expandability of the architecture are introduced as important factors influencing the network [8].
Compact AC Modeling of Eddy Current for Cylindrical Through Silicon Via
Published in IETE Journal of Research, 2021
Chopali Chanchal Sahu, Vijay Rao Kumbhare, Manoj Kumar Majumder
The component density of an integrated circuit (IC) follows Moore’s law to improve the performance and functionality of the system [1]. In order to meet the high-performance system requirements, the IC technology continues to scale down that exhibits new challenges such as higher interconnection density, more I/O pins, and lesser footprint area that primarily drives the researchers to move beyond the 2D IC. Therefore, in the recent past, the demand for 3D IC has increased as the dies are vertically stacked on top of each other that improves the performance of the system [2–4]. For interconnection purposes in 3D IC, through silicon via (TSV) is mostly used because it provides homogeneous as well as heterogeneous integration, larger bandwidths, and more cost-effective than wire bond technology. Mostly, copper is used as filler material in the TSV due to its higher conductivity and compatibility in via last TSV fabrication process. Additionally, Cu provides lower stress, void-free filling, good thermal cycling performance, conductivity, and higher current density than tungsten and polymer [5,6]. However, at higher frequencies, the electromagnetic field of Cu-based TSVs is varying due to the flow of an alternating current. Thus, a circulating current, popularly known as an eddy current, flows through the TSVs due to a relative motion between the electromagnetic field and other conducting layers at high frequencies. Therefore, it is required to consider an eddy resistance while modeling an equivalent RLGC model of TSV. The eddy resistance primarily arises due to the flow of eddy current in the conducting layers such as the depletion layer, silicon substrate, and neighboring TSVs [7].
Cu metallisation on glass substrate with through glass via using wet plating process
Published in Transactions of the IMF, 2021
M. Takayama, K. Inoue, H. Honma, M. Watanabe
With the advent of the IoT (Internet of Things) era, enormous amounts of data are being successively accumulated through network connections. The range of application of large amount of data is being widened, and it will significantly change our lives and societies. Research and development of large-capacity and high-speed data communication technology as well as various sensors is being conducted as these comprise critical technology to realise new societies. Also, remarkable progress is being seen in new materials and nano-processing technology. In the field of electronics, finer patterning and higher integration are further promoted and high-performance circuit boards are required. Even greater insulating materials properties improvements and electronic device performances are being sought.1 The development of circuit boards using silicon for semiconductors is being pursued. In recent years, through silicon via (TSV)2 that has vias formed in silicon has been developed. Advances in semiconductor technology have made it possible to improve the degree of integration; for example, vertically stacking chips on a TSV substrate enabled the change from planar integration to three-dimensional integration of large scale integration (LSI). Accordingly, advanced packaging methods are being developed including 3D/2.5D packaging,3 Fan-Out4 that forms a redistribution layer on top of the wafer and expands (fans out) the contacts beyond the dimensions of the chip, and Embedded Multi die Interconnect Bridge (EMIB)5 that uses a very small silicon die with multiple routing layers, that serves as an in-package interconnect. For electronic devices, thin and small semiconductor devices that are integrated at high density and can operate at high speed will continuously be required.