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Screening
Published in Michael G. Pecht, Riko Radojcic, Gopal Rao, Guidebook for Managing Silicon Chip Reliability, 2017
Michael G. Pecht, Riko Radojcic, Gopal Rao
IDDQ testing is capable of detecting inter-level shorts, multiple stuck-at-faults, pinholes, spot defects and soft defects [Al-Assadi, 1996]. IDDQ can identify a wide range of failure types including those undetectable by stuck-at-fault testing. Such types include parasitic transistor leakage, gate-oxide defects, bridging defects, leaky p-n junction, and transistor faults [Al-Assadi, 1996; Wantuk, 1996]. These faults have a tendency to cause elevated quiescent power supply current, which is detectable by IDDQ. The effectiveness of the IDDQ screen is measured through IDDQ coverage, defined here as the percentage of nodes held in both states (logical “0” and “1”) during IDDQ measurements.
VLSI Design and Testability
Published in Manoj Kumar Majumder, Vijay Rao Kumbhare, Aditya Japa, Brajesh Kumar Kaushik, Introduction to Microelectronics to Nanoelectronics, 2020
Manoj Kumar Majumder, Vijay Rao Kumbhare, Aditya Japa, Brajesh Kumar Kaushik
The presence of manufacturing fault can also be identified in CMOS integrated circuit using IDDQ testing. This technique allows the current to flow such that the fault can easily be identified in the quiescent state. Figure 8.7 shows a general block diagram of IDDQ testing, where the detection of fault can be observed by monitoring the IDDQ current. In order to have a faster and accurate analysis, the IDDQ test should be very sensitive [17].
Fault tolerant system based on IDDQ testing
Published in International Journal of Electronics, 2018
Badi Guibane, Belgacem Hamdi, Abdellatif Mtibaa, Brahim Bensalem
To increase the reliability of integrated circuits, fault-tolerant architectures can be a solution to tolerate faults (Fang & Hsiao, 2006; Koren & Krishna, 2007; Vial et al., 2008, 2009). Several works in the field of fault-tolerant systems have been published. The majority of reported works have been designed to improve the reliability of digital circuits (Almukhaizim & Makris, 2003; Ashkan, Yaghini, Pedram, & Zarandi, 2010; Ban, Alves, & Naviner, 2010; Kshirsagar & Patrikar, 2009; Palaka & Rao, 2012). For the design of analogue and mixed signal integrated circuit’s fault-tolerant systems, only a handful of works have been reported. Askari (2010) presented scalable mean voter for fault-tolerant mixed-signal circuits. On the other hand, the quiescent current supply (IDDQ) testing has proved to be very effective in testing defective circuits (Ashok, Alli, Yellampali & Rajput 2009; Sotiris, Yiorgos, Angela, & Themistoklis, 2015). The technique monitors power supply current through the power supply pins of the integrated circuit. If the power supply current is not within the normal range, a defect is reported (Jeong, 2010; Jeong, Sung, & Jong, 2010). A built-in current sensor can be integrated in the circuit to monitor the power supply current. IDDQ test has been initially considered for the use in the complex CMOS circuits during the manufacturing stage or during the end-test stage. This technique allows the detection of design errors. For the case where the current sensor is integrated on-chip, the sensor is released after the testing for defects has ended. This technique can be extended to an online test to detect and mask the permanent and transient faults.